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Searched refs:in_reg (Results 1 – 9 of 9) sorted by relevance

/external/llvm-project/llvm/test/CodeGen/AArch64/
Darm64-big-endian-varargs.ll33 br i1 %inreg, label %vaarg.in_reg, label %vaarg.on_stack
35 vaarg.in_reg: ; preds = %vaarg.maybe_reg
52 vaarg.end: ; preds = %vaarg.on_stack, %vaarg.in_reg
53 %.sink = phi i8* [ %4, %vaarg.in_reg ], [ %stack, %vaarg.on_stack ]
/external/llvm/test/CodeGen/AArch64/
Darm64-big-endian-varargs.ll33 br i1 %inreg, label %vaarg.in_reg, label %vaarg.on_stack
35 vaarg.in_reg: ; preds = %vaarg.maybe_reg
52 vaarg.end: ; preds = %vaarg.on_stack, %vaarg.in_reg
53 %.sink = phi i8* [ %4, %vaarg.in_reg ], [ %stack, %vaarg.on_stack ]
/external/llvm-project/llvm/test/CodeGen/X86/
Dx32-va_start.ll49 br i1 %fits_in_gp, label %vaarg.in_reg, label %vaarg.in_mem
53 vaarg.in_reg: ; preds = %entry
77 vaarg.end: ; preds = %vaarg.in_mem, %vaarg.in_reg
78 %vaarg.addr.in = phi i8* [ %2, %vaarg.in_reg ], [ %overflow_arg_area, %vaarg.in_mem ]
/external/llvm/test/CodeGen/X86/
Dx32-va_start.ll49 br i1 %fits_in_gp, label %vaarg.in_reg, label %vaarg.in_mem
53 vaarg.in_reg: ; preds = %entry
77 vaarg.end: ; preds = %vaarg.in_mem, %vaarg.in_reg
78 %vaarg.addr.in = phi i8* [ %2, %vaarg.in_reg ], [ %overflow_arg_area, %vaarg.in_mem ]
/external/llvm-project/llvm/test/Instrumentation/MemorySanitizer/X86/
Dvararg_call.ll69 br i1 %fits_in_gp, label %vaarg.in_reg, label %vaarg.in_mem
71 vaarg.in_reg: ; preds = %for.body
85 vaarg.end: ; preds = %vaarg.in_mem, %vaarg.in_reg
86 %gp_offset12 = phi i32 [ %4, %vaarg.in_reg ], [ %gp_offset, %vaarg.in_mem ]
87 %vaarg.addr.in = phi i8* [ %3, %vaarg.in_reg ], [ %overflow_arg_area, %vaarg.in_mem ]
/external/llvm-project/llvm/test/CodeGen/Hexagon/
Dvararg_align_check.ll69 br i1 %2, label %vaarg.on_stack, label %vaarg.in_reg
71 vaarg.in_reg: ; preds = %vaarg.maybe_reg
89 vaarg.end: ; preds = %vaarg.on_stack, %vaarg.in_reg
90 %vaarg.addr = phi i64* [ %3, %vaarg.in_reg ], [ %5, %vaarg.on_stack ]
Dvararg_double_onstack.ll54 br i1 %1, label %vaarg.on_stack, label %vaarg.in_reg
56 vaarg.in_reg: ; preds = %vaarg.maybe_reg
74 vaarg.end: ; preds = %vaarg.on_stack, %vaarg.in_reg
75 %vaarg.addr = phi i64* [ %2, %vaarg.in_reg ], [ %4, %vaarg.on_stack ]
Dvararg_named.ll71 br i1 %4, label %vaarg.on_stack, label %vaarg.in_reg
73 vaarg.in_reg: ; preds = %vaarg.maybe_reg
87 vaarg.end: ; preds = %vaarg.on_stack, %vaarg.in_reg
88 %vaarg.addr = phi i32* [ %5, %vaarg.in_reg ], [ %6, %vaarg.on_stack ]
/external/skia/src/core/
DSkVM.cpp3388 auto in_reg = [&](Val v) -> bool { in jit() local
3621 if (in_reg(x)) { a->vaddps(dst(x), r(x), any(y)); } in jit()
3626 if (in_reg(x)) { a->vmulps(dst(x), r(x), any(y)); } in jit()
3663 if (in_reg(x)) { a->vsqrtps(dst(x), r(x)); } in jit()
3668 if (in_reg(x)) { a->vpaddd(dst(x), r(x), any(y)); } in jit()
3673 if (in_reg(x)) { a->vpmulld(dst(x), r(x), any(y)); } in jit()
3680 if (in_reg(x)) { a->vpand(dst(x), r(x), any(y)); } in jit()
3684 if (in_reg(x)) { a->vpor(dst(x), r(x), any(y)); } in jit()
3688 if (in_reg(x)) { a->vpxor(dst(x), r(x), any(y)); } in jit()
3704 if (in_reg(x)) { a->vpcmpeqd(dst(x), r(x), any(y)); } in jit()
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