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Searched refs:insert0 (Results 1 – 7 of 7) sorted by relevance

/external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/
DshlN_add.ll367 %insert0 = insertvalue { i32, i32 } undef, i32 %shl, 0
368 %insert1 = insertvalue { i32, i32 } %insert0, i32 %add, 1
380 %insert0 = insertvalue { i32, i32 } undef, i32 %shl, 0
381 %insert1 = insertvalue { i32, i32 } %insert0, i32 %add, 1
393 %insert0 = insertvalue { i32, i32 } undef, i32 %shl, 0
394 %insert1 = insertvalue { i32, i32 } %insert0, i32 %add, 1
407 %insert0 = insertvalue { i32, i32 } undef, i32 %shl, 0
408 %insert1 = insertvalue { i32, i32 } %insert0, i32 %add, 1
/external/javassist/src/main/javassist/bytecode/
DCodeIterator.java340 return insert0(currentPos, code, false); in insert()
365 insert0(pos, code, false); in insert()
389 return insert0(pos, code, false); in insertAt()
413 return insert0(currentPos, code, true); in insertEx()
438 insert0(pos, code, true); in insertEx()
462 return insert0(pos, code, true); in insertExAt()
469 private int insert0(int pos, byte[] code, boolean exclusive) in insert0() method in CodeIterator
/external/llvm/test/Transforms/SROA/
Dbig-endian.ll38 ; CHECK-NEXT: %[[insert0:.*]] = or i24 %[[mask0]], %[[shift0]]
50 ; CHECK: %[[shift0:.*]] = lshr i24 %[[insert0]], 16
52 ; CHECK-NEXT: %[[shift1:.*]] = lshr i24 %[[insert0]], 8
54 ; CHECK-NEXT: %[[trunc2:.*]] = trunc i24 %[[insert0]] to i8
Dbasictest.ll605 ; CHECK-NEXT: %[[insert0:.*]] = or i24 %[[mask0]], %[[ext0]]
617 ; CHECK: %[[trunc0:.*]] = trunc i24 %[[insert0]] to i8
618 ; CHECK-NEXT: %[[shift1:.*]] = lshr i24 %[[insert0]], 8
620 ; CHECK-NEXT: %[[shift2:.*]] = lshr i24 %[[insert0]], 16
/external/llvm-project/llvm/test/Transforms/SROA/
Dbig-endian.ll38 ; CHECK-NEXT: %[[insert0:.*]] = or i24 %[[mask0]], %[[shift0]]
50 ; CHECK: %[[shift0:.*]] = lshr i24 %[[insert0]], 16
52 ; CHECK-NEXT: %[[shift1:.*]] = lshr i24 %[[insert0]], 8
54 ; CHECK-NEXT: %[[trunc2:.*]] = trunc i24 %[[insert0]] to i8
Dbasictest.ll685 ; CHECK-NEXT: %[[insert0:.*]] = or i24 %[[mask0]], %[[ext0]]
697 ; CHECK: %[[trunc0:.*]] = trunc i24 %[[insert0]] to i8
698 ; CHECK-NEXT: %[[shift1:.*]] = lshr i24 %[[insert0]], 8
700 ; CHECK-NEXT: %[[shift2:.*]] = lshr i24 %[[insert0]], 16
/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dpacked-op-sel.ll678 %insert0 = insertelement <2 x half> undef, half %shl.bc, i32 0
681 %insert1 = shufflevector <2 x half> %fadd, <2 x half> %insert0, <2 x i32> <i32 1, i32 0>