| /external/mesa3d/src/compiler/nir/ |
| D | nir_intrinsics.py | 171 def intrinsic(name, src_comp=[], dest_comp=-1, indices=[], function
177 intrinsic("nop", flags=[CAN_ELIMINATE])
179 intrinsic("convert_alu_types", dest_comp=0, src_comp=[0],
183 intrinsic("load_param", dest_comp=0, indices=[PARAM_IDX], flags=[CAN_ELIMINATE])
185 intrinsic("load_deref", dest_comp=0, src_comp=[-1],
187 intrinsic("store_deref", src_comp=[-1, 0], indices=[WRMASK, ACCESS])
188 intrinsic("copy_deref", src_comp=[-1, -1], indices=[DST_ACCESS, SRC_ACCESS])
189 intrinsic("memcpy_deref", src_comp=[-1, -1, 1], indices=[DST_ACCESS, SRC_ACCESS])
197 intrinsic("interp_deref_at_centroid", dest_comp=0, src_comp=[1],
199 intrinsic("interp_deref_at_sample", src_comp=[1, 1], dest_comp=0,
[all …]
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| D | nir_lower_wrmasks.c | 62 value_src(nir_intrinsic_op intrinsic) in value_src() argument
64 switch (intrinsic) { in value_src()
78 offset_src(nir_intrinsic_op intrinsic) in offset_src() argument
80 switch (intrinsic) { in offset_src()
97 const nir_intrinsic_info *info = &nir_intrinsic_infos[intr->intrinsic]; in split_wrmask()
104 unsigned value_idx = value_src(intr->intrinsic); in split_wrmask()
105 unsigned offset_idx = offset_src(intr->intrinsic); in split_wrmask()
124 nir_intrinsic_instr_create(b->shader, intr->intrinsic); in split_wrmask()
206 if (value_src(intr->intrinsic) < 0) in nir_lower_wrmasks_instr()
209 assert(offset_src(intr->intrinsic) >= 0); in nir_lower_wrmasks_instr()
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| D | nir_lower_io_arrays_to_elements.c | 120 if (intr->intrinsic != nir_intrinsic_store_deref) { in lower_array()
173 nir_intrinsic_instr_create(b->shader, intr->intrinsic); in lower_array()
177 if (intr->intrinsic != nir_intrinsic_store_deref) { in lower_array()
181 if (intr->intrinsic == nir_intrinsic_interp_deref_at_offset || in lower_array()
182 intr->intrinsic == nir_intrinsic_interp_deref_at_sample || in lower_array()
183 intr->intrinsic == nir_intrinsic_interp_deref_at_vertex) { in lower_array()
244 if (intr->intrinsic != nir_intrinsic_load_deref && in create_indirects_mask()
245 intr->intrinsic != nir_intrinsic_store_deref && in create_indirects_mask()
246 intr->intrinsic != nir_intrinsic_interp_deref_at_centroid && in create_indirects_mask()
247 intr->intrinsic != nir_intrinsic_interp_deref_at_sample && in create_indirects_mask()
[all …]
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| /external/mesa3d/src/compiler/spirv/tests/ |
| D | volatile.cpp | 76 nir_intrinsic_instr *intrinsic = find_intrinsic(nir_intrinsic_load_deref); in TEST_F() local
77 ASSERT_NE(intrinsic, nullptr); in TEST_F()
78 EXPECT_NE(nir_intrinsic_access(intrinsic) & ACCESS_VOLATILE, 0); in TEST_F()
132 nir_intrinsic_instr *intrinsic = find_intrinsic(nir_intrinsic_store_deref); in TEST_F() local
133 ASSERT_NE(intrinsic, nullptr); in TEST_F()
134 EXPECT_NE(nir_intrinsic_access(intrinsic) & ACCESS_VOLATILE, 0); in TEST_F()
186 nir_intrinsic_instr *intrinsic = find_intrinsic(nir_intrinsic_load_deref); in TEST_F() local
187 ASSERT_NE(intrinsic, nullptr); in TEST_F()
188 EXPECT_NE(nir_intrinsic_access(intrinsic) & ACCESS_VOLATILE, 0); in TEST_F()
190 intrinsic = find_intrinsic(nir_intrinsic_store_deref); in TEST_F()
[all …]
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| D | avail_vis.cpp | 80 nir_intrinsic_instr *intrinsic = find_intrinsic(nir_intrinsic_scoped_barrier, 0); in TEST_F() local
81 ASSERT_NE(intrinsic, nullptr); in TEST_F()
83 …EXPECT_EQ(nir_intrinsic_memory_semantics(intrinsic), NIR_MEMORY_MAKE_VISIBLE | NIR_MEMORY_ACQUIRE); in TEST_F()
84 EXPECT_NE(nir_intrinsic_memory_modes(intrinsic) & nir_var_mem_ssbo, 0); in TEST_F()
85 EXPECT_EQ(nir_intrinsic_memory_scope(intrinsic), NIR_SCOPE_DEVICE); in TEST_F()
86 EXPECT_EQ(nir_intrinsic_execution_scope(intrinsic), NIR_SCOPE_NONE); in TEST_F()
144 nir_intrinsic_instr *intrinsic = find_intrinsic(nir_intrinsic_scoped_barrier, 0); in TEST_F() local
145 ASSERT_NE(intrinsic, nullptr); in TEST_F()
147 …EXPECT_EQ(nir_intrinsic_memory_semantics(intrinsic), NIR_MEMORY_MAKE_AVAILABLE | NIR_MEMORY_RELEAS… in TEST_F()
148 EXPECT_NE(nir_intrinsic_memory_modes(intrinsic) & nir_var_mem_ssbo, 0); in TEST_F()
[all …]
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| /external/llvm-project/llvm/include/llvm/IR/ |
| D | CMakeLists.txt | 5 tablegen(LLVM IntrinsicImpl.inc -gen-intrinsic-impl)
6 tablegen(LLVM IntrinsicEnums.inc -gen-intrinsic-enums)
7 tablegen(LLVM IntrinsicsAArch64.h -gen-intrinsic-enums -intrinsic-prefix=aarch64)
8 tablegen(LLVM IntrinsicsAMDGPU.h -gen-intrinsic-enums -intrinsic-prefix=amdgcn)
9 tablegen(LLVM IntrinsicsARM.h -gen-intrinsic-enums -intrinsic-prefix=arm)
10 tablegen(LLVM IntrinsicsBPF.h -gen-intrinsic-enums -intrinsic-prefix=bpf)
11 tablegen(LLVM IntrinsicsHexagon.h -gen-intrinsic-enums -intrinsic-prefix=hexagon)
12 tablegen(LLVM IntrinsicsMips.h -gen-intrinsic-enums -intrinsic-prefix=mips)
13 tablegen(LLVM IntrinsicsNVPTX.h -gen-intrinsic-enums -intrinsic-prefix=nvvm)
14 tablegen(LLVM IntrinsicsPowerPC.h -gen-intrinsic-enums -intrinsic-prefix=ppc)
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/IR/ |
| D | CMakeLists.txt | 5 tablegen(LLVM IntrinsicImpl.inc -gen-intrinsic-impl)
6 tablegen(LLVM IntrinsicEnums.inc -gen-intrinsic-enums)
7 tablegen(LLVM IntrinsicsAArch64.h -gen-intrinsic-enums -intrinsic-prefix=aarch64)
8 tablegen(LLVM IntrinsicsAMDGPU.h -gen-intrinsic-enums -intrinsic-prefix=amdgcn)
9 tablegen(LLVM IntrinsicsARM.h -gen-intrinsic-enums -intrinsic-prefix=arm)
10 tablegen(LLVM IntrinsicsBPF.h -gen-intrinsic-enums -intrinsic-prefix=bpf)
11 tablegen(LLVM IntrinsicsHexagon.h -gen-intrinsic-enums -intrinsic-prefix=hexagon)
12 tablegen(LLVM IntrinsicsMips.h -gen-intrinsic-enums -intrinsic-prefix=mips)
13 tablegen(LLVM IntrinsicsNVPTX.h -gen-intrinsic-enums -intrinsic-prefix=nvvm)
14 tablegen(LLVM IntrinsicsPowerPC.h -gen-intrinsic-enums -intrinsic-prefix=ppc)
[all …]
|
| /external/llvm-project/llvm/utils/gn/secondary/llvm/include/llvm/IR/ |
| D | BUILD.gn | 10 args = [ "-gen-intrinsic-impl" ]
16 args = [ "-gen-intrinsic-enums" ]
24 "-gen-intrinsic-enums",
25 "-intrinsic-prefix=aarch64",
34 "-gen-intrinsic-enums",
35 "-intrinsic-prefix=amdgcn",
44 "-gen-intrinsic-enums",
45 "-intrinsic-prefix=arm",
54 "-gen-intrinsic-enums",
55 "-intrinsic-prefix=bpf",
[all …]
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| /external/llvm-project/llvm/test/Assembler/ |
| D | immarg-param-attribute.ll | 3 ; CHECK: declare void @llvm.test.immarg.intrinsic.i32(i32 immarg)
4 declare void @llvm.test.immarg.intrinsic.i32(i32 immarg)
6 ; CHECK: declare void @llvm.test.immarg.intrinsic.f32(float immarg)
7 declare void @llvm.test.immarg.intrinsic.f32(float immarg)
9 ; CHECK-LABEL: @call_llvm.test.immarg.intrinsic.i32(
10 define void @call_llvm.test.immarg.intrinsic.i32() {
11 ; CHECK: call void @llvm.test.immarg.intrinsic.i32(i32 0)
12 call void @llvm.test.immarg.intrinsic.i32(i32 0)
14 ; CHECK: call void @llvm.test.immarg.intrinsic.i32(i32 0)
15 call void @llvm.test.immarg.intrinsic.i32(i32 0)
[all …]
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| /external/llvm-project/llvm/test/Verifier/ |
| D | immarg-param-attribute-invalid.ll | 3 declare void @llvm.test.immarg.intrinsic.i32(i32 immarg)
4 declare void @llvm.test.immarg.intrinsic.v2i32(<2 x i32> immarg)
5 declare void @llvm.test.immarg.intrinsic.f32(float immarg)
6 declare void @llvm.test.immarg.intrinsic.v2f32(<2 x float> immarg)
7 declare void @llvm.test.immarg.intrinsic.2ai32([2 x i32] immarg)
11 define void @call_llvm.test.immarg.intrinsic.i32(i32 %arg) {
14 ; CHECK-NEXT: call void @llvm.test.immarg.intrinsic.i32(i32 undef)
15 call void @llvm.test.immarg.intrinsic.i32(i32 undef)
19 ; CHECK-NEXT: call void @llvm.test.immarg.intrinsic.i32(i32 %arg)
20 call void @llvm.test.immarg.intrinsic.i32(i32 %arg)
[all …]
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| /external/llvm-project/clang/test/Preprocessor/ |
| D | pragma_microsoft.c | 177 #pragma intrinsic(memset) // no-warning
178 #pragma intrinsic(memcpy, strlen, strlen) // no-warning
179 #pragma intrinsic() // no-warning
180 #pragma intrinsic(asdf) // expected-warning {{'asdf' is not a recognized builtin; consider includin…
181 #pragma intrinsic(main) // expected-warning {{'main' is not a recognized builtin; consider includin…
182 #pragma intrinsic( // expected-warning {{missing ')' after}}
183 #pragma intrinsic(int) // expected-warning {{missing ')' after}}
184 #pragma intrinsic(strcmp) asdf // expected-warning {{extra tokens at end}}
187 #pragma intrinsic(asdf) // expected-warning-re {{'asdf' is not a recognized builtin{{$}}}}
188 #pragma intrinsic(memset) // no-warning
[all …]
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| /external/mesa3d/src/freedreno/ir3/ |
| D | ir3_nir_lower_io_offsets.c | 46 get_ir3_intrinsic_for_ssbo_intrinsic(unsigned intrinsic, in get_ir3_intrinsic_for_ssbo_intrinsic() argument
53 switch (intrinsic) { in get_ir3_intrinsic_for_ssbo_intrinsic()
165 lower_offset_for_ssbo(nir_intrinsic_instr *intrinsic, nir_builder *b, in lower_offset_for_ssbo() argument
168 unsigned num_srcs = nir_intrinsic_infos[intrinsic->intrinsic].num_srcs; in lower_offset_for_ssbo()
171 bool has_dest = nir_intrinsic_infos[intrinsic->intrinsic].has_dest; in lower_offset_for_ssbo()
175 if ((has_dest && intrinsic->dest.ssa.bit_size == 16) || in lower_offset_for_ssbo()
176 (!has_dest && intrinsic->src[0].ssa->bit_size == 16)) in lower_offset_for_ssbo()
184 b->cursor = nir_before_instr(&intrinsic->instr); in lower_offset_for_ssbo()
190 debug_assert(intrinsic->src[offset_src_idx].is_ssa); in lower_offset_for_ssbo()
191 nir_ssa_def *offset = intrinsic->src[offset_src_idx].ssa; in lower_offset_for_ssbo()
[all …]
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| /external/mesa3d/src/gallium/drivers/zink/ |
| D | nir_lower_dynamic_bo_access.c | 49 unsigned block_idx = instr->intrinsic == nir_intrinsic_store_ssbo; in recursive_generate_bo_ssa_def()
50 nir_intrinsic_instr *new_instr = nir_intrinsic_instr_create(b->shader, instr->intrinsic); in recursive_generate_bo_ssa_def()
52 for (unsigned i = 0; i < nir_intrinsic_infos[instr->intrinsic].num_srcs; i++) { in recursive_generate_bo_ssa_def()
56 if (instr->intrinsic != nir_intrinsic_load_ubo_vec4) { in recursive_generate_bo_ssa_def()
58 if (instr->intrinsic != nir_intrinsic_load_ssbo) in recursive_generate_bo_ssa_def()
62 if (instr->intrinsic != nir_intrinsic_store_ssbo) in recursive_generate_bo_ssa_def()
81 if (instr->intrinsic != nir_intrinsic_load_ubo && in lower_dynamic_bo_access_instr()
82 instr->intrinsic != nir_intrinsic_load_ubo_vec4 && in lower_dynamic_bo_access_instr()
83 instr->intrinsic != nir_intrinsic_get_ssbo_size && in lower_dynamic_bo_access_instr()
84 instr->intrinsic != nir_intrinsic_load_ssbo && in lower_dynamic_bo_access_instr()
[all …]
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| /external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/ |
| D | legalize-fdiv.mir | 29 …; SI: [[INT:%[0-9]+]]:_(s32), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scal…
30 …; SI: [[INT2:%[0-9]+]]:_(s32), [[INT3:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.sca…
31 ; SI: [[INT4:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[INT]](s32)
39 …; SI: [[INT5:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[FMA4]](s32), [[FMA…
40 …; SI: [[INT6:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](s32), [[FP…
51 ; VI: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[FPEXT1]](s32)
54 …; VI: [[INT1:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[FPTRUNC]](s16), […
64 ; GFX9: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[FPEXT1]](s32)
67 …; GFX9: [[INT1:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[FPTRUNC]](s16),…
75 ; GFX9-UNSAFE: [[INT:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[TRUNC1]](s16)
[all …]
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| D | legalize-fcos.mir | 16 ; SI: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s32)
17 ; SI: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT]](s32)
23 ; VI: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s32)
24 ; VI: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT]](s32)
30 ; GFX9: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[FMUL]](s32)
47 ; SI: [[INT:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s64)
48 ; SI: [[INT1:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT]](s64)
54 ; VI: [[INT:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s64)
55 ; VI: [[INT1:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT]](s64)
61 ; GFX9: [[INT:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[FMUL]](s64)
[all …]
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| D | legalize-fsin.mir | 16 ; SI: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s32)
17 ; SI: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT]](s32)
23 ; VI: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s32)
24 ; VI: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT]](s32)
30 ; GFX9: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[FMUL]](s32)
47 ; SI: [[INT:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s64)
48 ; SI: [[INT1:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT]](s64)
54 ; VI: [[INT:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s64)
55 ; VI: [[INT1:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT]](s64)
61 ; GFX9: [[INT:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[FMUL]](s64)
[all …]
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| D | regbankselect-amdgcn.readlane.mir | 16 …; CHECK: [[INT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readlane), [[COPY2]](s32),…
19 %2:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readlane), %0, %1
32 …; CHECK: [[INT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readlane), [[COPY]](s32), …
35 %2:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readlane), %0, %1
49 …; CHECK: [[INT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readlane), [[COPY]](s32), …
52 %2:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readlane), %0, %1
67 …; CHECK: [[INT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readlane), [[COPY2]](s32),…
70 %2:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readlane), %0, %1
86 …; CHECK: [[INT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readlane), [[COPY2]](s32),…
90 %2:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readlane), %0, %1
[all …]
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| D | legalize-amdgcn.if-invalid.mir | 3 …rol flow intrinsics fails to select in case some transform separated the intrinsic from its branch.
5 … legalize instruction: %3:_(s1), %4:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if)…
6 … legalize instruction: %3:_(s1), %4:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if)…
7 … legalize instruction: %3:_(s1), %4:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if)…
8 … legalize instruction: %3:_(s1), %4:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if)…
9 … legalize instruction: %3:_(s1), %4:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if)…
10 … legalize instruction: %3:_(s1), %4:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if)…
22 %3:_(s1), %4:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if), %2
37 %3:_(s1), %4:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if), %2
51 %3:_(s1), %4:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if), %2
[all …]
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| /external/llvm-project/flang/test/Semantics/ |
| D | resolve46.f90 | 4 intrinsic :: cos ! a specific & generic intrinsic name
5 intrinsic :: alog10 ! a specific intrinsic name, not generic
6 intrinsic :: null ! a weird special case
7 intrinsic :: bessel_j0 ! generic intrinsic, not specific
8 intrinsic :: amin0
10 intrinsic :: haltandcatchfire
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| /external/llvm-project/llvm/test/MachineVerifier/ |
| D | test_g_intrinsic.mir | 20 ; CHECK: Bad machine code: G_INTRINSIC first src operand must be an intrinsic ID
23 ; CHECK: Bad machine code: G_INTRINSIC first src operand must be an intrinsic ID
26 ; CHECK: Bad machine code: G_INTRINSIC first src operand must be an intrinsic ID
29 ; CHECK: Bad machine code: G_INTRINSIC first src operand must be an intrinsic ID
32 ; CHECK: Bad machine code: G_INTRINSIC used with intrinsic that accesses memory
33 G_INTRINSIC intrinsic(@llvm.amdgcn.s.barrier)
35 ; CHECK: Bad machine code: G_INTRINSIC used with intrinsic that accesses memory
36 %3:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.ds.append), %0, 1
|
| /external/mesa3d/src/intel/compiler/ |
| D | brw_nir_lower_cs_intrinsics.c | 50 nir_intrinsic_instr *intrinsic = nir_instr_as_intrinsic(instr); in lower_cs_intrinsics_convert_block() local
52 b->cursor = nir_after_instr(&intrinsic->instr); in lower_cs_intrinsics_convert_block()
55 switch (intrinsic->intrinsic) { in lower_cs_intrinsics_convert_block()
60 if (intrinsic->dest.ssa.bit_size == 64) { in lower_cs_intrinsics_convert_block()
61 intrinsic->dest.ssa.bit_size = 32; in lower_cs_intrinsics_convert_block()
62 sysval = nir_u2u64(b, &intrinsic->dest.ssa); in lower_cs_intrinsics_convert_block()
63 nir_ssa_def_rewrite_uses_after(&intrinsic->dest.ssa, in lower_cs_intrinsics_convert_block()
154 if (intrinsic->intrinsic == nir_intrinsic_load_local_invocation_id) in lower_cs_intrinsics_convert_block()
187 if (intrinsic->dest.ssa.bit_size == 64) in lower_cs_intrinsics_convert_block()
190 nir_ssa_def_rewrite_uses(&intrinsic->dest.ssa, nir_src_for_ssa(sysval)); in lower_cs_intrinsics_convert_block()
[all …]
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| /external/llvm-project/compiler-rt/lib/sanitizer_common/ |
| D | sanitizer_atomic_msvc.h | 18 #pragma intrinsic(_ReadWriteBarrier)
20 #pragma intrinsic(_mm_mfence)
22 #pragma intrinsic(_mm_pause)
24 #pragma intrinsic(_InterlockedExchange8)
26 #pragma intrinsic(_InterlockedExchange16)
28 #pragma intrinsic(_InterlockedExchange)
30 #pragma intrinsic(_InterlockedExchangeAdd)
33 #pragma intrinsic(_InterlockedCompareExchange8)
36 #pragma intrinsic(_InterlockedCompareExchange16)
39 #pragma intrinsic(_InterlockedCompareExchange64)
[all …]
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| /external/mesa3d/src/compiler/glsl/ |
| D | gl_nir_lower_samplers_as_deref.c | 286 if (instr->intrinsic == nir_intrinsic_image_deref_load || in lower_intrinsic()
287 instr->intrinsic == nir_intrinsic_image_deref_store || in lower_intrinsic()
288 instr->intrinsic == nir_intrinsic_image_deref_atomic_add || in lower_intrinsic()
289 instr->intrinsic == nir_intrinsic_image_deref_atomic_imin || in lower_intrinsic()
290 instr->intrinsic == nir_intrinsic_image_deref_atomic_umin || in lower_intrinsic()
291 instr->intrinsic == nir_intrinsic_image_deref_atomic_imax || in lower_intrinsic()
292 instr->intrinsic == nir_intrinsic_image_deref_atomic_umax || in lower_intrinsic()
293 instr->intrinsic == nir_intrinsic_image_deref_atomic_and || in lower_intrinsic()
294 instr->intrinsic == nir_intrinsic_image_deref_atomic_or || in lower_intrinsic()
295 instr->intrinsic == nir_intrinsic_image_deref_atomic_xor || in lower_intrinsic()
[all …]
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| /external/llvm-project/llvm/utils/TableGen/ |
| D | IntrinsicEmitter.cpp | 634 const CodeGenIntrinsic &intrinsic = Ints[i]; in EmitAttributes() local
636 std::max(maxArgAttrs, unsigned(intrinsic.ArgumentAttributes.size())); in EmitAttributes()
637 unsigned &N = UniqAttributes[&intrinsic]; in EmitAttributes()
648 const CodeGenIntrinsic &intrinsic = Ints[i]; in EmitAttributes() local
650 OS << " " << UniqAttributes[&intrinsic] << ", // " in EmitAttributes()
651 << intrinsic.Name << "\n"; in EmitAttributes()
664 const CodeGenIntrinsic &intrinsic = *(I->first); in EmitAttributes() local
670 unsigned ai = 0, ae = intrinsic.ArgumentAttributes.size(); in EmitAttributes()
673 unsigned attrIdx = intrinsic.ArgumentAttributes[ai].Index; in EmitAttributes()
681 switch (intrinsic.ArgumentAttributes[ai].Kind) { in EmitAttributes()
[all …]
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| /external/mesa3d/src/gallium/auxiliary/gallivm/ |
| D | lp_bld_arit.c | 98 const char *intrinsic = NULL; in lp_build_min_simple() local
110 intrinsic = "llvm.x86.sse.min.ss"; in lp_build_min_simple()
114 intrinsic = "llvm.x86.sse.min.ps"; in lp_build_min_simple()
118 intrinsic = "llvm.x86.avx.min.ps.256"; in lp_build_min_simple()
124 intrinsic = "llvm.x86.sse2.min.sd"; in lp_build_min_simple()
128 intrinsic = "llvm.x86.sse2.min.pd"; in lp_build_min_simple()
132 intrinsic = "llvm.x86.avx.min.pd.256"; in lp_build_min_simple()
144 intrinsic = "llvm.ppc.altivec.vminfp"; in lp_build_min_simple()
151 intrinsic = "llvm.ppc.altivec.vminub"; in lp_build_min_simple()
153 intrinsic = "llvm.ppc.altivec.vminsb"; in lp_build_min_simple()
[all …]
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