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/external/skia/gn/
Dsksl_tests.gni249 "/sksl/intrinsics/AbsFloat.sksl",
250 "/sksl/intrinsics/AbsInt.sksl",
251 "/sksl/intrinsics/Acos.sksl",
252 "/sksl/intrinsics/Acosh.sksl",
253 "/sksl/intrinsics/All.sksl",
254 "/sksl/intrinsics/Any.sksl",
255 "/sksl/intrinsics/Asin.sksl",
256 "/sksl/intrinsics/Asinh.sksl",
257 "/sksl/intrinsics/Atan.sksl",
258 "/sksl/intrinsics/Atanh.sksl",
[all …]
/external/llvm-project/llvm/docs/Proposals/
DVectorPredication.rst17 masked loads and stores, are available through intrinsics [MaskedIR]_.
27 1. IR-level VP intrinsics
31 - VP intrinsics and attributes are available on IR level.
41 - VP intrinsics translate to first-class SDNodes
52 that match standard vector IR and VP intrinsics.
59 Result: Optimization of VP intrinsics on par with standard vector instructions.
67 Result: VP has superseded earlier vector intrinsics.
74 - Phase out VP intrinsics, only keeping those that are not equivalent to
84 .. [MaskedIR] `llvm.masked.*` intrinsics,
85 https://llvm.org/docs/LangRef.html#masked-vector-load-and-store-intrinsics
/external/llvm-project/mlir/test/mlir-tblgen/
Dllvm-intrinsics.td4 // platform-specific intrinsics, so we need to give it to TableGen instead of
9 // We also verify emission of type specialization for overloadable intrinsics.
13 // RUN: | mlir-tblgen -gen-llvmir-intrinsics -I %S/../../../llvm/include/ --llvmir-intrinsics-filte…
37 // RUN: | mlir-tblgen -gen-llvmir-intrinsics -I %S/../../../llvm/include/ --llvmir-intrinsics-filte…
45 // RUN: | mlir-tblgen -gen-llvmir-intrinsics -I %S/../../../llvm/include/ --llvmir-intrinsics-filte…
/external/llvm-project/flang/include/flang/Lower/
DBridge.h57 const Fortran::evaluate::IntrinsicProcTable &intrinsics, in create() argument
59 return LoweringBridge{defaultKinds, intrinsics, allCooked}; in create()
72 return intrinsics; in getIntrinsicTable()
101 const Fortran::evaluate::IntrinsicProcTable &intrinsics,
107 const Fortran::evaluate::IntrinsicProcTable &intrinsics; variable
/external/libopus/m4/
Dopus-intrinsics.m41 dnl opus-intrinsics.m4
2 dnl macro for testing for support for compiler intrinsics, either by default or with a compiler flag
7 AC_MSG_CHECKING([if compiler supports $1 intrinsics])
17 AC_MSG_CHECKING([if compiler supports $1 intrinsics with $2])
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/IR/
DIntrinsicsWebAssembly.td1 //===- IntrinsicsWebAssembly.td - Defines wasm intrinsics --*- tablegen -*-===//
10 /// This file defines all of the WebAssembly-specific intrinsics.
14 let TargetPrefix = "wasm" in { // All intrinsics start with "llvm.wasm.".
49 // Exception handling intrinsics
78 // Atomic intrinsics
100 // SIMD intrinsics
171 // Bulk memory intrinsics
185 // Thread-local storage intrinsics
DIntrinsicsBPF.td1 //===- IntrinsicsBPF.td - Defines BPF intrinsics -----------*- tablegen -*-===//
9 // This file defines all of the BPF-specific intrinsics.
14 let TargetPrefix = "bpf" in { // All intrinsics start with "llvm.bpf."
DIntrinsicsPowerPC.td1 //===- IntrinsicsPowerPC.td - Defines PowerPC intrinsics ---*- tablegen -*-===//
9 // This file defines all of the PowerPC-specific intrinsics.
14 // Definitions for all PowerPC intrinsics.
17 // Non-altivec intrinsics.
18 let TargetPrefix = "ppc" in { // All intrinsics start with "llvm.ppc.".
96 let TargetPrefix = "ppc" in { // All PPC intrinsics start with "llvm.ppc.".
97 /// PowerPC_Vec_Intrinsic - Base class for all altivec intrinsics.
104 /// PowerPC_VSX_Intrinsic - Base class for all VSX intrinsics.
117 /// vector and returns one. These intrinsics have no side effects.
123 /// vectors and returns one. These intrinsics have no side effects.
[all …]
DIntrinsicsX86.td1 //===- IntrinsicsX86.td - Defines X86 intrinsics -----------*- tablegen -*-===//
9 // This file defines all of the X86-specific intrinsics.
15 let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
20 // SEH intrinsics for Windows
175 let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
203 let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
252 let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
272 let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
278 let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
294 let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
[all …]
DIntrinsicsRISCV.td1 //===- IntrinsicsRISCV.td - Defines RISCV intrinsics -------*- tablegen -*-===//
9 // This file defines all of the RISCV-specific intrinsics.
21 // In fact, as these intrinsics take `llvm_anyptr_ty`, the given names are the
22 // canonical names, and the intrinsics used in the code will have a name
/external/llvm-project/clang-tools-extra/docs/clang-tidy/checks/
Dportability-simd-intrinsics.rst1 .. title:: clang-tidy - portability-simd-intrinsics
3 portability-simd-intrinsics
6 Finds SIMD intrinsics calls and suggests ``std::experimental::simd`` (`P0214`_)
19 Otherwise, it just complains the intrinsics are non-portable (and there are
28 operations. By migrating from target-dependent intrinsics to `P0214`_
/external/libopus/
Dmeson.build166 opt_intrinsics = get_option('intrinsics')
187 # and 'presume we have this SIMD' by checking whether the SIMD / intrinsics can
189 # With MSVC, the compiler will always build SIMD/intrinsics targeting all
258 # The same rules apply for x86 assembly and intrinsics.
351 # Check for ARMv7/AArch64 neon intrinsics
361 name: 'compiler supports @0@ intrinsics'.format(intrin_name))
368 …name: 'compiler supports @0@ intrinsics with @1@'.format(intrin_name, ' '.join(arm_neon_intr_link_…
386 message('Compiler does not support @0@ intrinsics'.format(intrin_name))
389 # Check for aarch64 neon intrinsics
399 name: 'compiler supports @0@ intrinsics'.format(intrin_name))
[all …]
/external/llvm/include/llvm/IR/
DIntrinsicsWebAssembly.td1 //===- IntrinsicsWebAssembly.td - Defines wasm intrinsics --*- tablegen -*-===//
11 /// \brief This file defines all of the WebAssembly-specific intrinsics.
15 let TargetPrefix = "wasm" in { // All intrinsics start with "llvm.wasm.".
DIntrinsicsPowerPC.td1 //===- IntrinsicsPowerPC.td - Defines PowerPC intrinsics ---*- tablegen -*-===//
10 // This file defines all of the PowerPC-specific intrinsics.
15 // Definitions for all PowerPC intrinsics.
18 // Non-altivec intrinsics.
19 let TargetPrefix = "ppc" in { // All intrinsics start with "llvm.ppc.".
63 let TargetPrefix = "ppc" in { // All PPC intrinsics start with "llvm.ppc.".
64 /// PowerPC_Vec_Intrinsic - Base class for all altivec intrinsics.
71 /// PowerPC_VSX_Intrinsic - Base class for all VSX intrinsics.
84 /// vector and returns one. These intrinsics have no side effects.
90 /// vectors and returns one. These intrinsics have no side effects.
[all …]
DIntrinsicsBPF.td1 //===- IntrinsicsBPF.td - Defines BPF intrinsics -----------*- tablegen -*-===//
10 // This file defines all of the BPF-specific intrinsics.
15 let TargetPrefix = "bpf" in { // All intrinsics start with "llvm.bpf."
/external/llvm-project/llvm/include/llvm/IR/
DIntrinsicsWebAssembly.td1 //===- IntrinsicsWebAssembly.td - Defines wasm intrinsics --*- tablegen -*-===//
10 /// This file defines all of the WebAssembly-specific intrinsics.
14 let TargetPrefix = "wasm" in { // All intrinsics start with "llvm.wasm.".
49 // Exception handling intrinsics
78 // Atomic intrinsics
101 // SIMD intrinsics
165 // TODO: Replace these intrinsics with normal ISel patterns once i32x4 to i64x2
181 // TODO: Replace these intrinsics with normal ISel patterns
225 // These intrinsics do not mark their lane index arguments as immediate because
306 // Thread-local storage intrinsics
DIntrinsicsBPF.td1 //===- IntrinsicsBPF.td - Defines BPF intrinsics -----------*- tablegen -*-===//
9 // This file defines all of the BPF-specific intrinsics.
14 let TargetPrefix = "bpf" in { // All intrinsics start with "llvm.bpf."
DIntrinsicsVE.td1 // Define intrinsics written by hand
3 // Define intrinsics automatically generated
DIntrinsicsHexagon.td1 //===- IntrinsicsHexagon.td - Defines Hexagon intrinsics ---*- tablegen -*-===//
8 // This file defines all of the Hexagon-specific intrinsics.
13 // Definitions for all Hexagon intrinsics.
15 // All Hexagon intrinsics start with "llvm.hexagon.".
17 /// Hexagon_Intrinsic - Base class for the majority of Hexagon intrinsics.
25 /// intrinsics.
257 // These intrinsics do not emit (nor do they correspond to) any instructions,
DIntrinsicsX86.td1 //===- IntrinsicsX86.td - Defines X86 intrinsics -----------*- tablegen -*-===//
9 // This file defines all of the X86-specific intrinsics.
15 let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
20 // SEH intrinsics for Windows
175 let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
203 let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
252 let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
272 let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
278 let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
294 let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
[all …]
DConstrainedOps.def1 //===- llvm/IR/ConstrainedOps.def - Constrained intrinsics ------*- C++ -*-===//
9 // Defines properties of constrained intrinsics, in particular corresponding
50 // intrinsics.
70 // constrained intrinsics.
100 // constrained FMA or FMUL + FADD intrinsics.
DIntrinsicsRISCV.td1 //===- IntrinsicsRISCV.td - Defines RISCV intrinsics -------*- tablegen -*-===//
9 // This file defines all of the RISCV-specific intrinsics.
21 // In fact, as these intrinsics take `llvm_anyptr_ty`, the given names are the
22 // canonical names, and the intrinsics used in the code will have a name
/external/llvm/lib/Target/AMDGPU/
DAMDGPUIntrinsics.td1 //===-- AMDGPUIntrinsics.td - Common intrinsics -*- tablegen -*-----------===//
10 // This file defines intrinsics that are used by all hw codegen targets.
21 // Deprecated in favor of separate int_amdgcn_cube* intrinsics.
/external/llvm-project/flang/unittests/Evaluate/
Dfolding.cpp46 auto intrinsics{Fortran::evaluate::IntrinsicProcTable::Configure(defaults)}; in TestHostRuntimeSubnormalFlushing() local
48 messages, defaults, intrinsics, defaultRounding, true}; in TestHostRuntimeSubnormalFlushing()
50 messages, defaults, intrinsics, defaultRounding, false}; in TestHostRuntimeSubnormalFlushing()
/external/llvm-project/mlir/lib/Dialect/StandardOps/EDSC/
DIntrinsics.cpp15 BranchOp mlir::edsc::intrinsics::std_br(Block *block, ValueRange operands) { in std_br()
19 CondBranchOp mlir::edsc::intrinsics::std_cond_br(Value cond, Block *trueBranch, in std_cond_br()

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