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/external/llvm/lib/Target/ARM/
DARMInstrFormats.td352 class AsmPseudoInst<string asm, dag iops, dag oops = (outs)>
356 let InOperandList = iops;
363 class ARMAsmPseudo<string asm, dag iops, dag oops = (outs)>
364 : AsmPseudoInst<asm, iops, oops>, Requires<[IsARM]>;
365 class tAsmPseudo<string asm, dag iops, dag oops = (outs)>
366 : AsmPseudoInst<asm, iops, oops>, Requires<[IsThumb]>;
367 class t2AsmPseudo<string asm, dag iops, dag oops = (outs)>
368 : AsmPseudoInst<asm, iops, oops>, Requires<[IsThumb2]>;
369 class VFP2AsmPseudo<string asm, dag iops, dag oops = (outs)>
370 : AsmPseudoInst<asm, iops, oops>, Requires<[HasVFP2]>;
[all …]
DARMInstrThumb2.td295 class T2OneRegImm<dag oops, dag iops, InstrItinClass itin,
297 : T2I<oops, iops, itin, opc, asm, pattern> {
308 class T2sOneRegImm<dag oops, dag iops, InstrItinClass itin,
310 : T2sI<oops, iops, itin, opc, asm, pattern> {
321 class T2OneRegCmpImm<dag oops, dag iops, InstrItinClass itin,
323 : T2I<oops, iops, itin, opc, asm, pattern> {
334 class T2OneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
336 : T2I<oops, iops, itin, opc, asm, pattern> {
347 class T2sOneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
349 : T2sI<oops, iops, itin, opc, asm, pattern> {
[all …]
DARMInstrThumb.td837 class T1pIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
839 : T1pI<oops, iops, itin, opc, asm, pattern>,
846 class T1pIMiscEncode<bits<7> opA, dag oops, dag iops, InstrItinClass itin,
848 : T1pI<oops, iops, itin, opc, asm, pattern>,
857 class T1sIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
859 : T1sI<oops, iops, itin, opc, asm, pattern>,
866 class T1sIGenEncode<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
868 : T1sI<oops, iops, itin, opc, asm, pattern>,
877 class T1sIGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
879 : T1sI<oops, iops, itin, opc, asm, pattern>,
[all …]
DARMInstrVFP.td1201 bits<4> opcod4, dag oops, dag iops,
1204 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
1220 bits<4> opcod4, dag oops, dag iops,InstrItinClass itin,
1222 : AVConv1In<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
1236 bits<4> opcod4, dag oops, dag iops,
1239 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
1335 bits<4> opcod4, dag oops, dag iops,
1338 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
1354 bits<4> opcod4, dag oops, dag iops,
1357 : AVConv1In<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
[all …]
/external/llvm-project/llvm/lib/Target/ARM/
DARMInstrFormats.td465 class AsmPseudoInst<string asm, dag iops, dag oops = (outs)>
469 let InOperandList = iops;
477 class ARMAsmPseudo<string asm, dag iops, dag oops = (outs)>
478 : AsmPseudoInst<asm, iops, oops>, Requires<[IsARM]>;
479 class tAsmPseudo<string asm, dag iops, dag oops = (outs)>
480 : AsmPseudoInst<asm, iops, oops>, Requires<[IsThumb]>;
481 class t2AsmPseudo<string asm, dag iops, dag oops = (outs)>
482 : AsmPseudoInst<asm, iops, oops>, Requires<[IsThumb2]>;
483 class VFP2AsmPseudo<string asm, dag iops, dag oops = (outs)>
484 : AsmPseudoInst<asm, iops, oops>, Requires<[HasVFP2]>;
[all …]
DARMInstrCDE.td52 class CDE_Instr<bit acc, dag oops, dag iops, string asm, string cstr>
53 : Thumb2XI<oops, !con((ins p_imm:$coproc), iops),
70 class CDE_GPR_Instr<bit dual, bit acc, dag oops, dag iops,
72 : CDE_Instr<acc, oops, iops, asm, cstr>,
252 class CDE_FP_Vec_Instr<bit vec, bit acc, dag oops, dag iops, string asm, string cstr>
253 : CDE_Instr<acc, oops, iops, asm, cstr> {
259 class CDE_FP_Instr<bit acc, bit sz, dag oops, dag iops, string asm, string cstr>
260 : CDE_FP_Vec_Instr<0b0, acc, oops, iops, asm, cstr> {
265 class CDE_Vec_Instr<bit acc, dag oops, dag iops, string asm, string cstr,
268 !con(iops, (ins vpred:$vp)), asm,
DARMInstrThumb2.td436 class T2OneRegImm<dag oops, dag iops, InstrItinClass itin,
438 : T2I<oops, iops, itin, opc, asm, pattern> {
449 class T2sOneRegImm<dag oops, dag iops, InstrItinClass itin,
451 : T2sI<oops, iops, itin, opc, asm, pattern> {
462 class T2OneRegCmpImm<dag oops, dag iops, InstrItinClass itin,
464 : T2I<oops, iops, itin, opc, asm, pattern> {
475 class T2OneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
477 : T2I<oops, iops, itin, opc, asm, pattern> {
488 class T2sOneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
490 : T2sI<oops, iops, itin, opc, asm, pattern> {
[all …]
DARMInstrVFP.td1378 bits<4> opcod4, dag oops, dag iops,
1381 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
1398 bits<4> opcod4, dag oops, dag iops,InstrItinClass itin,
1400 : AVConv1In<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
1416 bits<4> opcod4, dag oops, dag iops,
1419 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
1530 bits<4> opcod4, dag oops, dag iops,
1533 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
1550 bits<4> opcod4, dag oops, dag iops,
1553 : AVConv1In<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
[all …]
DARMInstrMVE.td395 class MVE_MI<dag oops, dag iops, InstrItinClass itin, string asm,
397 : Thumb2XI<oops, iops, AddrModeNone, 4, itin, !strconcat(asm, "\t", ops), cstr,
407 class MVE_p<dag oops, dag iops, InstrItinClass itin, string iname,
410 : MVE_MI<oops, !con(iops, (ins vpred:$vp)), itin,
421 class MVE_f<dag oops, dag iops, InstrItinClass itin, string iname,
424 : MVE_p<oops, iops, itin, iname, suffix, ops, vpred, cstr, pattern> {
428 class MVE_MI_with_pred<dag oops, dag iops, InstrItinClass itin, string asm,
430 : Thumb2I<oops, iops, AddrModeNone, 4, itin, asm, !strconcat("\t", ops), cstr,
437 class MVE_VMOV_lane_base<dag oops, dag iops, InstrItinClass itin, string asm,
440 : Thumb2I<oops, iops, AddrModeNone, 4, itin, asm,
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMInstrFormats.td459 class AsmPseudoInst<string asm, dag iops, dag oops = (outs)>
463 let InOperandList = iops;
471 class ARMAsmPseudo<string asm, dag iops, dag oops = (outs)>
472 : AsmPseudoInst<asm, iops, oops>, Requires<[IsARM]>;
473 class tAsmPseudo<string asm, dag iops, dag oops = (outs)>
474 : AsmPseudoInst<asm, iops, oops>, Requires<[IsThumb]>;
475 class t2AsmPseudo<string asm, dag iops, dag oops = (outs)>
476 : AsmPseudoInst<asm, iops, oops>, Requires<[IsThumb2]>;
477 class VFP2AsmPseudo<string asm, dag iops, dag oops = (outs)>
478 : AsmPseudoInst<asm, iops, oops>, Requires<[HasVFP2]>;
[all …]
DARMInstrThumb2.td435 class T2OneRegImm<dag oops, dag iops, InstrItinClass itin,
437 : T2I<oops, iops, itin, opc, asm, pattern> {
448 class T2sOneRegImm<dag oops, dag iops, InstrItinClass itin,
450 : T2sI<oops, iops, itin, opc, asm, pattern> {
461 class T2OneRegCmpImm<dag oops, dag iops, InstrItinClass itin,
463 : T2I<oops, iops, itin, opc, asm, pattern> {
474 class T2OneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
476 : T2I<oops, iops, itin, opc, asm, pattern> {
487 class T2sOneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
489 : T2sI<oops, iops, itin, opc, asm, pattern> {
[all …]
DARMInstrMVE.td357 class MVE_MI<dag oops, dag iops, InstrItinClass itin, string asm,
359 : Thumb2XI<oops, iops, AddrModeNone, 4, itin, !strconcat(asm, "\t", ops), cstr,
369 class MVE_p<dag oops, dag iops, InstrItinClass itin, string iname,
372 : MVE_MI<oops, !con(iops, (ins vpred:$vp)), itin,
383 class MVE_f<dag oops, dag iops, InstrItinClass itin, string iname,
386 : MVE_p<oops, iops, itin, iname, suffix, ops, vpred, cstr, pattern> {
390 class MVE_MI_with_pred<dag oops, dag iops, InstrItinClass itin, string asm,
392 : Thumb2I<oops, iops, AddrModeNone, 4, itin, asm, !strconcat("\t", ops), cstr,
399 class MVE_VMOV_lane_base<dag oops, dag iops, InstrItinClass itin, string asm,
402 : Thumb2I<oops, iops, AddrModeNone, 4, itin, asm,
[all …]
DARMInstrVFP.td1304 bits<4> opcod4, dag oops, dag iops,
1307 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
1323 bits<4> opcod4, dag oops, dag iops,InstrItinClass itin,
1325 : AVConv1In<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
1339 bits<4> opcod4, dag oops, dag iops,
1342 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
1452 bits<4> opcod4, dag oops, dag iops,
1455 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
1471 bits<4> opcod4, dag oops, dag iops,
1474 : AVConv1In<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
[all …]
/external/autotest/client/site_tests/platform_CryptohomeFio/
Dcontrol.stress22 'surfing': 'iops',
27 '16k_read': 'iops',
28 '16k_write': 'iops',
29 '8k_read': 'iops',
30 '8k_write': 'iops',
31 '4k_read': 'iops',
32 '4k_write': 'iops',
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/
DWebAssemblyInstrFormats.td31 class NI<dag oops, dag iops, list<dag> pattern, string stack,
35 dag InOperandList = iops;
41 // We have 2 sets of operands (oops & iops) for the register and stack
63 multiclass NRI<dag oops, dag iops, list<dag> pattern, string asmstr = "",
65 defm "": I<oops, iops, oops, iops, pattern, asmstr, asmstr, inst>;
/external/llvm-project/llvm/lib/Target/WebAssembly/
DWebAssemblyInstrFormats.td33 class NI<dag oops, dag iops, list<dag> pattern, string stack,
37 dag InOperandList = iops;
43 // We have 2 sets of operands (oops & iops) for the register and stack
65 multiclass NRI<dag oops, dag iops, list<dag> pattern, string asmstr = "",
67 defm "": I<oops, iops, oops, iops, pattern, asmstr, asmstr, inst>;
/external/mksh/src/
Dsyn.c271 struct ioword *iop, **iops; in get_command() local
277 iops = alloc2((NUFILE + 1), sizeof(struct ioword *), ATEMP); in get_command()
285 afree(iops, ATEMP); in get_command()
314 iops[iopn++] = iop; in get_command()
509 iops[iopn++] = iop; in get_command()
513 afree(iops, ATEMP); in get_command()
516 iops[iopn++] = NULL; in get_command()
517 iops = aresize2(iops, iopn, sizeof(struct ioword *), ATEMP); in get_command()
518 t->ioact = iops; in get_command()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DPPCScheduleP9.td35 // As iops are dispatched to a slice, they are held in an independent slice
59 // of the superslice, but are restricted to iops with only two primary sources.
134 // Vector ('V') - vector iops (128-bit operand) take only one decode and
149 // Paired ('P') - certain cracked and expanded iops are paired such that they
155 // Tuple Restricted ('R') - certain iops preclude dispatching more than one
161 // Each execution and branch slice can receive up to two iops per cycle
/external/llvm-project/llvm/lib/Target/PowerPC/
DPPCScheduleP9.td35 // As iops are dispatched to a slice, they are held in an independent slice
60 // of the superslice, but are restricted to iops with only two primary sources.
135 // Vector ('V') - vector iops (128-bit operand) take only one decode and
150 // Paired ('P') - certain cracked and expanded iops are paired such that they
156 // Tuple Restricted ('R') - certain iops preclude dispatching more than one
162 // Each execution and branch slice can receive up to two iops per cycle
/external/ltp/testcases/kernel/controllers/io-throttle/
Diobw.c61 static const char *iops[] = { variable
77 * 1000000L / 1024, iops[op]); in print_results()
/external/llvm/test/Bindings/llvm-c/
Decho.ll48 define i32 @iops(i32 %a, i32 %b) {
66 %1 = call i32 @iops(i32 23, i32 19)
/external/llvm/lib/Target/WebAssembly/
DWebAssemblyInstrFormats.td24 class I<dag oops, dag iops, list<dag> pattern, string asmstr = "">
27 dag InOperandList = iops;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64InstrFormats.td45 class Pseudo<dag oops, dag iops, list<dag> pattern, string cstr = "">
48 dag InOperandList = iops;
68 class I<dag oops, dag iops, string asm, string operands, string cstr,
72 dag InOperandList = iops;
1160 class BaseSystemI<bit L, dag oops, dag iops, string asm, string operands,
1162 : I<oops, iops, asm, operands, "", pattern> {
1168 class SimpleSystemI<bit L, dag iops, string asm, string operands,
1170 : BaseSystemI<L, (outs), iops, asm, operands, pattern> {
1175 class RtSystemI<bit L, dag oops, dag iops, string asm, string operands>
1176 : BaseSystemI<L, oops, iops, asm, operands>,
[all …]
/external/llvm-project/llvm/lib/Target/AArch64/
DAArch64InstrFormats.td79 class Pseudo<dag oops, dag iops, list<dag> pattern, string cstr = "">
82 dag InOperandList = iops;
95 class I<dag oops, dag iops, string asm, string operands, string cstr,
99 dag InOperandList = iops;
1284 class BaseSystemI<bit L, dag oops, dag iops, string asm, string operands,
1286 : I<oops, iops, asm, operands, "", pattern> {
1292 class SimpleSystemI<bit L, dag iops, string asm, string operands,
1294 : BaseSystemI<L, (outs), iops, asm, operands, pattern> {
1299 class RtSystemI<bit L, dag oops, dag iops, string asm, string operands>
1300 : BaseSystemI<L, oops, iops, asm, operands>,
[all …]
/external/llvm/lib/Target/AArch64/
DAArch64InstrFormats.td43 class Pseudo<dag oops, dag iops, list<dag> pattern, string cstr = "">
46 dag InOperandList = iops;
58 class I<dag oops, dag iops, string asm, string operands, string cstr,
62 dag InOperandList = iops;
834 class BaseSystemI<bit L, dag oops, dag iops, string asm, string operands,
836 : I<oops, iops, asm, operands, "", pattern> {
842 class SimpleSystemI<bit L, dag iops, string asm, string operands,
844 : BaseSystemI<L, (outs), iops, asm, operands, pattern> {
849 class RtSystemI<bit L, dag oops, dag iops, string asm, string operands>
850 : BaseSystemI<L, oops, iops, asm, operands>,
[all …]

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