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Searched refs:isInConsecutiveRegs (Results 1 – 17 of 17) sorted by relevance

/external/llvm/lib/Target/WebAssembly/
DWebAssemblyISelLowering.cpp317 if (Out.Flags.isInConsecutiveRegs()) in LowerCall()
409 if (In.Flags.isInConsecutiveRegs()) in LowerCall()
461 if (Out.Flags.isInConsecutiveRegs()) in LowerReturn()
489 if (In.Flags.isInConsecutiveRegs()) in LowerFormalArguments()
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DTargetCallingConv.h110 bool isInConsecutiveRegs() const { return IsInConsecutiveRegs; } in isInConsecutiveRegs() function
/external/llvm/include/llvm/Target/
DTargetCallingConv.h100 bool isInConsecutiveRegs() const { return Flags & InConsecutiveRegs; } in isInConsecutiveRegs() function
DTargetCallingConv.td57 class CCIfConsecutiveRegs<CCAction A> : CCIf<"ArgFlags.isInConsecutiveRegs()", A> {
/external/llvm-project/llvm/include/llvm/CodeGen/
DTargetCallingConv.h124 bool isInConsecutiveRegs() const { return IsInConsecutiveRegs; } in isInConsecutiveRegs() function
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/
DWebAssemblyISelLowering.cpp728 if (Out.Flags.isInConsecutiveRegs()) in LowerCall()
836 if (In.Flags.isInConsecutiveRegs()) in LowerCall()
896 if (Out.Flags.isInConsecutiveRegs()) in LowerReturn()
924 if (In.Flags.isInConsecutiveRegs()) in LowerFormalArguments()
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/
DAArch64GenCallingConv.inc143 if (ArgFlags.isInConsecutiveRegs()) {
441 if (ArgFlags.isInConsecutiveRegs()) {
753 if (ArgFlags.isInConsecutiveRegs()) {
1003 if (ArgFlags.isInConsecutiveRegs()) {
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Target/
DTargetCallingConv.td61 class CCIfConsecutiveRegs<CCAction A> : CCIf<"ArgFlags.isInConsecutiveRegs()", A> {
/external/llvm-project/llvm/include/llvm/Target/
DTargetCallingConv.td66 class CCIfConsecutiveRegs<CCAction A> : CCIf<"ArgFlags.isInConsecutiveRegs()", A> {
/external/llvm-project/llvm/lib/Target/WebAssembly/
DWebAssemblyISelLowering.cpp877 if (Out.Flags.isInConsecutiveRegs()) in LowerCall()
1008 if (In.Flags.isInConsecutiveRegs()) in LowerCall()
1064 if (Out.Flags.isInConsecutiveRegs()) in LowerReturn()
1096 if (In.Flags.isInConsecutiveRegs()) in LowerFormalArguments()
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/
DARMGenCallingConv.inc271 if (ArgFlags.isInConsecutiveRegs()) {
/external/llvm/lib/Target/PowerPC/
DPPCISelLowering.cpp2743 if (!Flags.isInConsecutiveRegs()) in CalculateStackSlotSize()
2780 if (Flags.isInConsecutiveRegs()) { in CalculateStackSlotAlignment()
3420 ArgSize = Flags.isInConsecutiveRegs() ? ObjSize : PtrByteSize; in LowerFormalArguments_64SVR4()
5386 } else if (!Flags.isInConsecutiveRegs()) { in LowerCall_64SVR4()
5422 !isLittleEndian && !Flags.isInConsecutiveRegs()) { in LowerCall_64SVR4()
5438 Flags.isInConsecutiveRegs()) ? 4 : 8; in LowerCall_64SVR4()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DPPCISelLowering.cpp3335 if (!Flags.isInConsecutiveRegs()) in CalculateStackSlotSize()
3372 if (Flags.isInConsecutiveRegs()) { in CalculateStackSlotAlignment()
4032 ArgSize = Flags.isInConsecutiveRegs() ? ObjSize : PtrByteSize; in LowerFormalArguments_64SVR4()
6247 } else if (!Flags.isInConsecutiveRegs()) { in LowerCall_64SVR4()
6283 !isLittleEndian && !Flags.isInConsecutiveRegs()) { in LowerCall_64SVR4()
6301 Flags.isInConsecutiveRegs()) ? 4 : 8; in LowerCall_64SVR4()
/external/llvm-project/llvm/lib/Target/PowerPC/
DPPCISelLowering.cpp3601 if (!Flags.isInConsecutiveRegs()) in CalculateStackSlotSize()
3634 if (Flags.isInConsecutiveRegs()) { in CalculateStackSlotAlignment()
4278 ArgSize = Flags.isInConsecutiveRegs() ? ObjSize : PtrByteSize; in LowerFormalArguments_64SVR4()
6449 } else if (!Flags.isInConsecutiveRegs()) { in LowerCall_64SVR4()
6485 !isLittleEndian && !Flags.isInConsecutiveRegs()) { in LowerCall_64SVR4()
6503 Flags.isInConsecutiveRegs()) ? 4 : 8; in LowerCall_64SVR4()
/external/llvm-project/llvm/lib/Target/AArch64/
DAArch64ISelLowering.cpp4563 !Ins[i].Flags.isInConsecutiveRegs()) in LowerFormalArguments()
4611 if (Ins[i].Flags.isInConsecutiveRegs()) { in LowerFormalArguments()
5291 if (Outs[i].Flags.isInConsecutiveRegs()) { in LowerCall()
5387 !Flags.isInConsecutiveRegs()) { in LowerCall()
/external/llvm/lib/Target/AArch64/
DAArch64ISelLowering.cpp2557 !Ins[i].Flags.isInConsecutiveRegs()) in LowerFormalArguments()
3106 !Flags.isInConsecutiveRegs()) { in LowerCall()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64ISelLowering.cpp3459 !Ins[i].Flags.isInConsecutiveRegs()) in LowerFormalArguments()
4151 !Flags.isInConsecutiveRegs()) { in LowerCall()