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Searched refs:isMoveReg (Results 1 – 25 of 52) sorted by relevance

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/external/llvm-project/llvm/include/llvm/MC/
DMCInstrDesc.h268 bool isMoveReg() const { return Flags & (1ULL << MCID::MoveReg); } in isMoveReg() function
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/MC/
DMCInstrDesc.h283 bool isMoveReg() const { return Flags & (1ULL << MCID::MoveReg); } in isMoveReg() function
/external/llvm-project/llvm/utils/TableGen/
DCodeGenInstruction.h243 bool isMoveReg : 1; variable
DInstrInfoEmitter.cpp752 if (Inst.isMoveReg) OS << "|(1ULL<<MCID::MoveReg)"; in emitRecord()
DCodeGenInstruction.cpp380 isMoveReg = R->getValueAsBit("isMoveReg"); in CodeGenInstruction()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsInstrFPU.td163 let isMoveReg = 1;
170 let isMoveReg = 1;
557 let isMoveReg = 1 in {
561 } // isMoveReg
DMips16InstrInfo.cpp101 if (MI.isMoveReg()) in isCopyInstrImpl()
DMipsDSPInstrInfo.td457 bit isMoveReg = 1;
468 bit isMoveReg = 1;
512 bit isMoveReg = 1;
522 bit isMoveReg = 1;
DMicroMipsInstrInfo.td239 let isMoveReg = 1;
405 let isMoveReg = 1;
412 let isMoveReg = 1;
DMicroMipsInstrFPU.td132 let isMoveReg = 1;
DMips16InstrInfo.td870 let isMoveReg = 1;
881 let isMoveReg = 1;
892 let isMoveReg = 0;
DMipsSEInstrInfo.cpp238 } else if (MI.isMoveReg() || isORCopyInst(MI)) { in isCopyInstrImpl()
/external/llvm-project/llvm/lib/Target/Mips/
DMipsInstrFPU.td166 let isMoveReg = 1;
173 let isMoveReg = 1;
590 let isMoveReg = 1 in {
594 } // isMoveReg
DMips16InstrInfo.cpp101 if (MI.isMoveReg()) in isCopyInstrImpl()
DMipsDSPInstrInfo.td457 bit isMoveReg = 1;
468 bit isMoveReg = 1;
512 bit isMoveReg = 1;
522 bit isMoveReg = 1;
DMicroMipsInstrInfo.td239 let isMoveReg = 1;
405 let isMoveReg = 1;
412 let isMoveReg = 1;
DMicroMipsInstrFPU.td132 let isMoveReg = 1;
DMips16InstrInfo.td870 let isMoveReg = 1;
881 let isMoveReg = 1;
892 let isMoveReg = 0;
DMipsSEInstrInfo.cpp238 } else if (MI.isMoveReg() || isORCopyInst(MI)) { in isCopyInstrImpl()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86InstrMMX.td212 let SchedRW = [WriteVecMove], hasSideEffects = 0, isMoveReg = 1 in {
219 } // SchedRW, hasSideEffects, isMoveReg
/external/llvm-project/llvm/lib/Target/X86/
DX86InstrMMX.td200 let SchedRW = [WriteVecMove], hasSideEffects = 0, isMoveReg = 1 in {
207 } // SchedRW, hasSideEffects, isMoveReg
/external/llvm-project/llvm/lib/Target/RISCV/
DRISCVInstrInfo.cpp557 if (MI.isMoveReg()) in isCopyInstrImpl()
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DMachineInstr.h755 bool isMoveReg(QueryType Type = IgnoreBundle) const {
/external/llvm-project/llvm/include/llvm/CodeGen/
DMachineInstr.h860 bool isMoveReg(QueryType Type = IgnoreBundle) const {
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMInstrVFP.td1041 let isMoveReg = 1 in {
1051 } // isMoveReg
1070 let isMoveReg = 1 in {
1117 } // isMoveReg

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