| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | DAGCombiner.cpp | 988 if (!TLI.isOperationLegal(ISD::ANY_EXTEND, PVT)) in PromoteOperand()
994 if (!TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, PVT)) in SExtPromoteOperand()
1726 if ((!LegalOperations || TLI.isOperationLegal(ISD::OR, VT)) && in visitADD()
1760 !TLI.isOperationLegal(ISD::SIGN_EXTEND, MVT::i1)) { in visitADD()
1847 if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) in tryFoldToZero()
2494 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { in visitMULHS()
2530 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { in visitMULHU()
2562 TLI.isOperationLegal(HiOp, N->getValueType(1)))) { in SimplifyNodeWithTwoResults()
2578 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType()))) in SimplifyNodeWithTwoResults()
2588 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType()))) in SimplifyNodeWithTwoResults()
[all …]
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| D | TargetLowering.cpp | 1606 (isOperationLegal(ISD::SETCC, newVT) && in SimplifySetCC()
2853 if (IsAfterLegalization ? isOperationLegal(ISD::MULHS, VT) : in BuildSDIV()
2857 else if (IsAfterLegalization ? isOperationLegal(ISD::SMUL_LOHI, VT) : in BuildSDIV()
2931 if (IsAfterLegalization ? isOperationLegal(ISD::MULHU, VT) : in BuildUDIV()
2934 else if (IsAfterLegalization ? isOperationLegal(ISD::UMUL_LOHI, VT) : in BuildUDIV()
|
| D | LegalizeIntegerTypes.cpp | 426 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) && in PromoteIntRes_FP_TO_XINT()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | DAGCombiner.cpp | 688 return TLI.isOperationLegal(Opcode, VT); in hasOperation()
1140 if (!TLI.isOperationLegal(ISD::ANY_EXTEND, PVT)) in PromoteOperand()
1146 if (!TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, PVT)) in SExtPromoteOperand()
2147 (TLI.isOperationLegal(ISD::XOR, X.getValueType()) && in visitADDLike()
2148 TLI.isOperationLegal(ISD::ZERO_EXTEND, VT))) && in visitADDLike()
2316 if ((!LegalOperations || TLI.isOperationLegal(ISD::OR, VT)) && in visitADD()
2946 if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) in tryFoldToZero()
2999 if (!LegalOperations || TLI.isOperationLegal(NewSh, VT)) in visitSUB()
4095 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { in visitMULHS()
4151 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { in visitMULHU()
[all …]
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| D | TargetLowering.cpp | 1696 if (!TLO.LegalOperations() || isOperationLegal(Opc, VT)) in SimplifyDemandedBits()
1729 if (!TLO.LegalOperations() || isOperationLegal(Opc, VT)) in SimplifyDemandedBits()
1753 if (!TLO.LegalOperations() || isOperationLegal(Opc, VT)) in SimplifyDemandedBits()
3401 (isOperationLegal(ISD::SETCC, newVT) && in SimplifySetCC()
4782 if (IsAfterLegalization ? isOperationLegal(ISD::MULHS, VT) in BuildSDIV()
4785 else if (IsAfterLegalization ? isOperationLegal(ISD::SMUL_LOHI, VT) in BuildSDIV()
4902 if (IsAfterLegalization ? isOperationLegal(ISD::MULHU, VT) in BuildUDIV()
4905 if (IsAfterLegalization ? isOperationLegal(ISD::UMUL_LOHI, VT) in BuildUDIV()
5508 return isOperationLegal(ISD::ConstantFP, VT) || in isNegatibleForFree()
5520 if (isOperationLegal(ISD::ConstantFP, VT) && in isNegatibleForFree()
[all …]
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| D | LegalizeIntegerTypes.cpp | 518 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) && in PromoteIntRes_FP_TO_XINT()
523 !TLI.isOperationLegal(ISD::STRICT_FP_TO_UINT, NVT) && in PromoteIntRes_FP_TO_XINT()
|
| /external/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| D | DAGCombiner.cpp | 1249 if (!TLI.isOperationLegal(ISD::ANY_EXTEND, PVT)) in PromoteOperand()
1255 if (!TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, PVT)) in SExtPromoteOperand()
2333 (TLI.isOperationLegal(ISD::XOR, X.getValueType()) && in visitADDLike()
2334 TLI.isOperationLegal(ISD::ZERO_EXTEND, VT))) && in visitADDLike()
2503 if ((!LegalOperations || TLI.isOperationLegal(ISD::OR, VT)) && in visitADD()
3153 if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) in tryFoldToZero()
3204 if (!LegalOperations || TLI.isOperationLegal(NewSh, VT)) in visitSUB()
4369 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { in visitMULHS()
4426 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { in visitMULHU()
4502 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { in visitSMUL_LOHI()
[all …]
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| D | TargetLowering.cpp | 1867 if (!TLO.LegalOperations() || isOperationLegal(Opc, VT)) in SimplifyDemandedBits()
1905 if (!TLO.LegalOperations() || isOperationLegal(Opc, VT)) in SimplifyDemandedBits()
1929 if (!TLO.LegalOperations() || isOperationLegal(Opc, VT)) in SimplifyDemandedBits()
3401 if (VT.isVector() && TLI.isOperationLegal(ISD::CTPOP, CTVT)) in simplifySetCCWithCTPOP()
3706 (isOperationLegal(ISD::SETCC, newVT) && in SimplifySetCC()
5076 if (IsAfterLegalization ? isOperationLegal(ISD::MULHS, VT) in BuildSDIV()
5079 else if (IsAfterLegalization ? isOperationLegal(ISD::SMUL_LOHI, VT) in BuildSDIV()
5196 if (IsAfterLegalization ? isOperationLegal(ISD::MULHU, VT) in BuildUDIV()
5199 if (IsAfterLegalization ? isOperationLegal(ISD::UMUL_LOHI, VT) in BuildUDIV()
5817 isOperationLegal(ISD::ConstantFP, VT) || in getNegatedExpression()
[all …]
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| D | LegalizeIntegerTypes.cpp | 567 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) && in PromoteIntRes_FP_TO_XINT()
572 !TLI.isOperationLegal(ISD::STRICT_FP_TO_UINT, NVT) && in PromoteIntRes_FP_TO_XINT()
|
| D | LegalizeDAG.cpp | 2840 if (TLI.isOperationLegal(ISD::CTPOP, VT)) { in ExpandPARITY()
|
| /external/llvm-project/llvm/include/llvm/CodeGen/ |
| D | TargetLowering.h | 1107 return isOperationLegal(Op, VT);
1121 return isOperationLegal(Op, VT);
1135 return isOperationLegal(Op, VT);
1208 bool isOperationLegal(unsigned Op, EVT VT) const { in isOperationLegal() function
2702 return isOperationLegal(ISD::FMAD, N->getValueType(0)); in isFMADLegal()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | SwitchLoweringUtils.cpp | 283 if (!TLI->isOperationLegal(ISD::SHL, PTy)) in findBitTestClusters()
|
| /external/llvm-project/llvm/lib/CodeGen/ |
| D | SwitchLoweringUtils.cpp | 286 if (!TLI->isOperationLegal(ISD::SHL, PTy)) in findBitTestClusters()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | TargetLowering.h | 1056 bool isOperationLegal(unsigned Op, EVT VT) const { in isOperationLegal() function
2533 return isOperationLegal(ISD::FMAD, N->getValueType(0)); in isFMADLegalForFAddFSub()
|
| /external/llvm/include/llvm/Target/ |
| D | TargetLowering.h | 649 bool isOperationLegal(unsigned Op, EVT VT) const { in isOperationLegal() function
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | R600ISelLowering.cpp | 1899 if (!isOperationLegal(ISD::BUILD_VECTOR, VT)) in PerformDAGCombine()
|
| D | AMDGPUISelLowering.cpp | 2257 if (isOperationLegal(ISD::FTRUNC, VT)) in LowerFROUND()
3070 isOperationLegal(ISD::BUILD_VECTOR, MVT::v2i16)) { in performShlCombine()
|
| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | R600ISelLowering.cpp | 1905 if (!isOperationLegal(ISD::BUILD_VECTOR, VT)) in PerformDAGCombine()
|
| D | AMDGPUISelLowering.cpp | 3076 isOperationLegal(ISD::BUILD_VECTOR, MVT::v2i16)) { in performShlCombine()
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | R600ISelLowering.cpp | 2009 if (!isOperationLegal(ISD::BUILD_VECTOR, VT)) in PerformDAGCombine()
|
| /external/llvm-project/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 16430 if (isOperationLegal(ISD::FMA, VT)) { in getNegatedExpression()
16504 if (VT.isVector() && TLI.isOperationLegal(Opcode, VT) && in stripModuloOnShift()
16779 isOperationLegal(ISD::MUL, N->getValueType(0))) in combineMUL()
16871 if (!isOperationLegal(ISD::FMA, VT)) in combineFMALike()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86TargetTransformInfo.cpp | 3477 return TLI->isOperationLegal(IsSigned ? ISD::SDIVREM : ISD::UDIVREM, VT); in hasDivRemOp()
|
| D | X86ISelLowering.cpp | 5108 if (isOperationLegal(ISD::MUL, VT)) in decomposeMulByConstant()
8191 if (isAfterLegalize && !TLI.isOperationLegal(ISD::LOAD, VT)) in EltsFromConsecutiveLoads()
21592 TLI.isOperationLegal(ISD::UMIN, VT)) { in LowerVSETCC()
25782 if (Opcode == ISD::UADDSAT && !TLI.isOperationLegal(ISD::UMIN, VT)) { in LowerADDSAT_SUBSAT()
25788 if (Opcode == ISD::USUBSAT && !TLI.isOperationLegal(ISD::UMAX, VT)) { in LowerADDSAT_SUBSAT()
37847 if (!DAG.getTargetLoweringInfo().isOperationLegal(ISD::SUB, MaskVT)) in combineLogicBlendIntoConditionalNegate()
40140 if (TLI.isTypeLegal(VT) && TLI.isOperationLegal(ISD::CTPOP, VT)) in combineParity()
42020 TLI.isOperationLegal(SrcOpcode, VT) && in combineTruncatedArithmetic()
42021 !TLI.isOperationLegal(SrcOpcode, SrcVT)) in combineTruncatedArithmetic()
42027 if (TLI.isOperationLegal(SrcOpcode, VT) && in combineTruncatedArithmetic()
[all …]
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| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86TargetTransformInfo.cpp | 4405 return TLI->isOperationLegal(IsSigned ? ISD::SDIVREM : ISD::UDIVREM, VT); in hasDivRemOp()
|
| D | X86ISelLowering.cpp | 5247 if (isOperationLegal(ISD::MUL, VT)) in decomposeMulByConstant()
8483 if (isAfterLegalize && !TLI.isOperationLegal(ISD::LOAD, VT)) in EltsFromConsecutiveLoads()
22841 TLI.isOperationLegal(ISD::UMIN, VT)) { in LowerVSETCC()
26922 if (Opcode == ISD::USUBSAT && !TLI.isOperationLegal(ISD::UMAX, VT)) { in LowerADDSAT_SUBSAT()
40580 if (!DAG.getTargetLoweringInfo().isOperationLegal(ISD::SUB, MaskVT)) in combineLogicBlendIntoConditionalNegate()
45405 TLI.isOperationLegal(SrcOpcode, VT) && in combineTruncatedArithmetic()
45406 !TLI.isOperationLegal(SrcOpcode, SrcVT)) in combineTruncatedArithmetic()
45416 if (TLI.isOperationLegal(SrcOpcode, VT) && in combineTruncatedArithmetic()
46031 !isOperationLegal(ISD::FMA, VT)) in getNegatedExpression()
|