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Searched refs:isPredicable (Results 1 – 25 of 124) sorted by relevance

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/external/llvm-project/llvm/lib/Target/Hexagon/
DHexagonPseudo.td161 let isCall = 1, hasSideEffects = 1, isPredicable = 0,
178 isPredicable = 0 in
207 let isPredicable = 0; // !if(isPred, 0, 1);
220 isPredicable = 1, hasSideEffects = 0, InputType = "reg",
234 isCodeGenOnly = 1, Defs = [PC], Uses = [R28], isPredicable = 0 in
238 let isPseudo = 1, isCall = 1, isReturn = 1, isBarrier = 1, isPredicable = 0,
244 let isPseudo = 1, isCall = 1, isReturn = 1, isBarrier = 1, isPredicable = 0,
337 isPredicable = 1,
353 Defs = [R29, R30, R31, PC], isPredicable = 0, isAsmParserOnly = 1 in {
DHexagonExpandCondsets.cpp221 bool isPredicable(MachineInstr *MI);
723 bool HexagonExpandCondsets::isPredicable(MachineInstr *MI) { in isPredicable() function in HexagonExpandCondsets
724 if (HII->isPredicated(*MI) || !HII->isPredicable(*MI)) in isPredicable()
961 if (!DefI || !isPredicable(DefI)) in predicate()
1228 if (!RDef || !HII->isPredicable(*RDef)) { in coalesceSegments()
1239 if (!RDef || !HII->isPredicable(*RDef)) { in coalesceSegments()
DHexagonEarlyIfConv.cpp482 if (!HII->isPredicable(*Def1) || !HII->isPredicable(*Def3)) in computePhiCost()
681 return MI->mayStore() && HII->isPredicable(const_cast<MachineInstr&>(*MI)); in isPredicableStore()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonPseudo.td161 let isCall = 1, hasSideEffects = 1, isPredicable = 0,
178 isPredicable = 0 in
207 let isPredicable = 0; // !if(isPred, 0, 1);
220 isPredicable = 1, hasSideEffects = 0, InputType = "reg",
234 isCodeGenOnly = 1, Defs = [PC], Uses = [R28], isPredicable = 0 in
238 let isPseudo = 1, isCall = 1, isReturn = 1, isBarrier = 1, isPredicable = 0,
244 let isPseudo = 1, isCall = 1, isReturn = 1, isBarrier = 1, isPredicable = 0,
337 isPredicable = 1,
353 Defs = [R29, R30, R31, PC], isPredicable = 0, isAsmParserOnly = 1 in {
DHexagonExpandCondsets.cpp219 bool isPredicable(MachineInstr *MI);
722 bool HexagonExpandCondsets::isPredicable(MachineInstr *MI) { in isPredicable() function in HexagonExpandCondsets
723 if (HII->isPredicated(*MI) || !HII->isPredicable(*MI)) in isPredicable()
960 if (!DefI || !isPredicable(DefI)) in predicate()
1227 if (!RDef || !HII->isPredicable(*RDef)) { in coalesceSegments()
1238 if (!RDef || !HII->isPredicable(*RDef)) { in coalesceSegments()
/external/llvm/include/llvm/MC/
DMCInstrDesc.h264 bool isPredicable() const { return Flags & (1 << MCID::Predicable); } in isPredicable() function
538 if (isPredicable()) { in findFirstPredOperandIdx()
/external/llvm-project/llvm/include/llvm/MC/
DMCInstrDesc.h321 bool isPredicable() const { return Flags & (1ULL << MCID::Predicable); } in isPredicable() function
614 if (isPredicable()) { in findFirstPredOperandIdx()
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/MC/
DMCInstrDesc.h336 bool isPredicable() const { return Flags & (1ULL << MCID::Predicable); } in isPredicable() function
629 if (isPredicable()) { in findFirstPredOperandIdx()
/external/llvm/utils/TableGen/
DCodeGenInstruction.h140 bool isPredicable; variable
238 bool isPredicable : 1; variable
DCodeGenInstruction.cpp29 isPredicable = false; in CGIOperandList()
100 isPredicable = true; in CGIOperandList()
313 isPredicable = Operands.isPredicable || R->getValueAsBit("isPredicable"); in CodeGenInstruction()
/external/llvm/lib/Target/ARM/
DThumb2SizeReduction.cpp756 if (!NewMCID.isPredicable()) in ReduceTo2Addr()
760 SkipPred = !NewMCID.isPredicable(); in ReduceTo2Addr()
852 if (!NewMCID.isPredicable()) in ReduceToNarrow()
856 SkipPred = !NewMCID.isPredicable(); in ReduceToNarrow()
910 if (!MCID.isPredicable() && NewMCID.isPredicable()) in ReduceToNarrow()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DThumb2SizeReduction.cpp796 if (!NewMCID.isPredicable()) in ReduceTo2Addr()
800 SkipPred = !NewMCID.isPredicable(); in ReduceTo2Addr()
889 if (!NewMCID.isPredicable()) in ReduceToNarrow()
893 SkipPred = !NewMCID.isPredicable(); in ReduceToNarrow()
958 if (!MCID.isPredicable() && NewMCID.isPredicable()) in ReduceToNarrow()
/external/llvm-project/llvm/lib/Target/ARM/
DThumb2SizeReduction.cpp806 if (!NewMCID.isPredicable()) in ReduceTo2Addr()
810 SkipPred = !NewMCID.isPredicable(); in ReduceTo2Addr()
899 if (!NewMCID.isPredicable()) in ReduceToNarrow()
903 SkipPred = !NewMCID.isPredicable(); in ReduceToNarrow()
968 if (!MCID.isPredicable() && NewMCID.isPredicable()) in ReduceToNarrow()
/external/llvm-project/llvm/utils/TableGen/
DCodeGenInstruction.h152 bool isPredicable; variable
256 bool isPredicable : 1; variable
DCodeGenInstruction.cpp28 isPredicable = false; in CGIOperandList()
109 isPredicable = true; in CGIOperandList()
388 isPredicable = !R->getValueAsBit("isUnpredicable") && ( in CodeGenInstruction()
389 Operands.isPredicable || R->getValueAsBit("isPredicable")); in CodeGenInstruction()
DInstrDocsEmitter.cpp118 FLAG(isPredicable) in EmitInstrDocs()
/external/llvm/lib/Target/Hexagon/
DHexagonExpandCondsets.cpp256 bool isPredicable(MachineInstr *MI);
718 bool HexagonExpandCondsets::isPredicable(MachineInstr *MI) { in isPredicable() function in HexagonExpandCondsets
719 if (HII->isPredicated(*MI) || !HII->isPredicable(*MI)) in isPredicable()
969 if (!DefI || !isPredicable(DefI)) in predicate()
1234 if (!RDef || !HII->isPredicable(*RDef)) in coalesceSegments()
1240 if (!RDef || !HII->isPredicable(*RDef)) in coalesceSegments()
/external/llvm/lib/Target/SystemZ/
DSystemZInstrInfo.h176 bool isPredicable(MachineInstr &MI) const override;
/external/llvm/lib/Target/PowerPC/
DPPCInstrInfo.h245 bool isPredicable(MachineInstr &MI) const override;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/
DSystemZInstrInfo.h232 bool isPredicable(const MachineInstr &MI) const override;
/external/llvm-project/llvm/lib/Target/SystemZ/
DSystemZInstrInfo.h247 bool isPredicable(const MachineInstr &MI) const override;
/external/llvm/lib/Target/AMDGPU/
DR600InstrInfo.h176 bool isPredicable(MachineInstr &MI) const override;
/external/llvm-project/llvm/lib/Target/AMDGPU/
DR600InstrInfo.h182 bool isPredicable(const MachineInstr &MI) const override;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DR600InstrInfo.h182 bool isPredicable(const MachineInstr &MI) const override;
/external/llvm/include/llvm/Target/
DTargetInstrInfo.h1111 virtual bool isPredicable(MachineInstr &MI) const { in isPredicable() function
1112 return MI.getDesc().isPredicable(); in isPredicable()

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