| /external/llvm-project/llvm/unittests/ADT/ |
| D | APIntTest.cpp | 1761 TEST(APIntTest, isShiftedMask) { in TEST() argument
1762 EXPECT_FALSE(APInt(32, 0x01010101).isShiftedMask()); in TEST()
1763 EXPECT_TRUE(APInt(32, 0xf0000000).isShiftedMask()); in TEST()
1764 EXPECT_TRUE(APInt(32, 0xffff0000).isShiftedMask()); in TEST()
1765 EXPECT_TRUE(APInt(32, 0xff << 1).isShiftedMask()); in TEST()
1768 EXPECT_FALSE(APInt(N, 0).isShiftedMask()); in TEST()
1773 EXPECT_TRUE(MaskVal.isShiftedMask()); in TEST()
1777 EXPECT_TRUE(MaskVal.isShiftedMask()); in TEST()
1781 EXPECT_TRUE(MaskVal.isShiftedMask()); in TEST()
|
| /external/llvm/include/llvm/ADT/ |
| D | APInt.h | 1799 inline bool isShiftedMask(unsigned numBits, const APInt &APIVal) { in isShiftedMask() function
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelDAGToDAG.cpp | 2038 static bool isShiftedMask(uint64_t Mask, EVT VT) { in isShiftedMask() function
2083 if (!isShiftedMask(KnownZero.getZExtValue(), VT)) in tryBitfieldInsertOpFromOrAndImm()
2258 (isShiftedMask(Mask0Imm, VT) || isShiftedMask(Mask1Imm, VT))) { in tryBitfieldInsertOpFromOr()
2263 if (isShiftedMask(Mask0Imm, VT)) { in tryBitfieldInsertOpFromOr()
|
| /external/swiftshader/third_party/llvm-subzero/include/llvm/ADT/ |
| D | APInt.h | 1826 inline bool isShiftedMask(unsigned numBits, const APInt &APIVal) { in isShiftedMask() function
|
| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86InstCombineIntrinsic.cpp | 1002 if (MaskC->getValue().isShiftedMask()) { in instCombineIntrinsic()
1047 if (MaskC->getValue().isShiftedMask()) { in instCombineIntrinsic()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64ISelDAGToDAG.cpp | 2249 static bool isShiftedMask(uint64_t Mask, EVT VT) { in isShiftedMask() function
2293 if (!isShiftedMask(Known.Zero.getZExtValue(), VT)) in tryBitfieldInsertOpFromOrAndImm()
2467 (isShiftedMask(Mask0Imm, VT) || isShiftedMask(Mask1Imm, VT))) { in tryBitfieldInsertOpFromOr()
2472 if (isShiftedMask(Mask0Imm, VT)) { in tryBitfieldInsertOpFromOr()
|
| /external/llvm-project/llvm/include/llvm/ADT/ |
| D | APInt.h | 522 bool isShiftedMask() const {
|
| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/ADT/ |
| D | APInt.h | 521 bool isShiftedMask() const { in isShiftedMask() function
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 100 static bool isShiftedMask(uint64_t I, uint64_t &Pos, uint64_t &Size) { in isShiftedMask() function
802 !isShiftedMask(CN->getZExtValue(), SMPos, SMSize)) in performANDCombine()
884 !isShiftedMask(~CN->getSExtValue(), SMPos0, SMSize0)) in performORCombine()
892 !isShiftedMask(CN->getZExtValue(), SMPos1, SMSize1)) in performORCombine()
1137 !isShiftedMask(CN->getZExtValue(), SMPos, SMSize)) in performSHLCombine()
|
| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64ISelDAGToDAG.cpp | 2430 static bool isShiftedMask(uint64_t Mask, EVT VT) { in isShiftedMask() function
2474 if (!isShiftedMask(Known.Zero.getZExtValue(), VT)) in tryBitfieldInsertOpFromOrAndImm()
2648 (isShiftedMask(Mask0Imm, VT) || isShiftedMask(Mask1Imm, VT))) { in tryBitfieldInsertOpFromOr()
2653 if (isShiftedMask(Mask0Imm, VT)) { in tryBitfieldInsertOpFromOr()
|
| /external/llvm-project/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 100 static bool isShiftedMask(uint64_t I, uint64_t &Pos, uint64_t &Size) { in isShiftedMask() function
803 !isShiftedMask(CN->getZExtValue(), SMPos, SMSize)) in performANDCombine()
885 !isShiftedMask(~CN->getSExtValue(), SMPos0, SMSize0)) in performORCombine()
893 !isShiftedMask(CN->getZExtValue(), SMPos1, SMSize1)) in performORCombine()
1138 !isShiftedMask(CN->getZExtValue(), SMPos, SMSize)) in performSHLCombine()
|
| /external/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 65 static bool isShiftedMask(uint64_t I, uint64_t &Pos, uint64_t &Size) { in isShiftedMask() function
708 !isShiftedMask(CN->getZExtValue(), SMPos, SMSize)) in performANDCombine()
743 !isShiftedMask(~CN->getSExtValue(), SMPos0, SMSize0)) in performORCombine()
751 !isShiftedMask(CN->getZExtValue(), SMPos1, SMSize1)) in performORCombine()
|
| /external/llvm-project/llvm/lib/Transforms/InstCombine/ |
| D | InstCombineAddSub.cpp | 983 C2->isNegative() && C2->isShiftedMask() && *C == (*C & *C2)) { in foldAddWithConstant()
|
| /external/llvm/lib/Transforms/InstCombine/ |
| D | InstCombineAndOrXor.cpp | 340 if (!APIntOps::isShiftedMask(BitWidth, V)) return false; in isRunOfOnes()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelLowering.cpp | 3164 if (Mask->getAPIntValue().isShiftedMask() && in performSrlCombine()
|
| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelLowering.cpp | 3170 if (Mask->getAPIntValue().isShiftedMask() && in performSrlCombine()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | DAGCombiner.cpp | 10405 } else if (Mask.isShiftedMask()) { in ReduceLoadWidth()
|
| /external/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| D | DAGCombiner.cpp | 11355 } else if (Mask.isShiftedMask()) { in ReduceLoadWidth()
|