| /external/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| D | AArch64PostLegalizerCombiner.cpp | 108 static bool isSignExtended(Register R, MachineRegisterInfo &MRI) { in isSignExtended() function
152 (isSignExtended(LHS, MRI) || isZeroExtended(LHS, MRI))) in matchAArch64MulConstCombine()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.h | 411 bool isSignExtended(const MachineInstr &MI, const unsigned depth = 0) const {
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| D | PPCMIPeephole.cpp | 665 TII->isSignExtended(*SrcMI)) { in simplifyCode()
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| D | PPCInstrInfo.cpp | 1662 if (isSignExtended(*MI)) in optimizeCompareInstr()
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| /external/llvm-project/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.h | 575 bool isSignExtended(const MachineInstr &MI, const unsigned depth = 0) const {
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| D | PPCMIPeephole.cpp | 828 TII->isSignExtended(*SrcMI)) { in simplifyCode()
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| D | PPCInstrInfo.cpp | 1964 if (isSignExtended(*MI)) in optimizeCompareInstr()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 2173 static bool isSignExtended(SDNode *N, SelectionDAG &DAG) { in isSignExtended() function
2195 isSignExtended(N0, DAG) && isSignExtended(N1, DAG); in isAddSubSExt()
2221 bool isN0SExt = isSignExtended(N0, DAG); in LowerMUL()
2222 bool isN1SExt = isSignExtended(N1, DAG); in LowerMUL()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 2821 static bool isSignExtended(SDNode *N, SelectionDAG &DAG) { in isSignExtended() function
2837 isSignExtended(N0, DAG) && isSignExtended(N1, DAG); in isAddSubSExt()
2883 bool isN0SExt = isSignExtended(N0, DAG); in LowerMUL()
2884 bool isN1SExt = isSignExtended(N1, DAG); in LowerMUL()
9785 if (N0->hasOneUse() && (isSignExtended(N0.getNode(), DAG) || in performMulCombine()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 6489 static bool isSignExtended(SDNode *N, SelectionDAG &DAG) { in isSignExtended() function
6619 isSignExtended(N0, DAG) && isSignExtended(N1, DAG); in isAddSubSExt()
6645 bool isN0SExt = isSignExtended(N0, DAG); in LowerMUL()
6646 bool isN1SExt = isSignExtended(N1, DAG); in LowerMUL()
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| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 3377 static bool isSignExtended(SDNode *N, SelectionDAG &DAG) { in isSignExtended() function
3393 isSignExtended(N0, DAG) && isSignExtended(N1, DAG); in isAddSubSExt()
3449 bool isN0SExt = isSignExtended(N0, DAG); in LowerMUL()
3450 bool isN1SExt = isSignExtended(N1, DAG); in LowerMUL()
11647 if (N0->hasOneUse() && (isSignExtended(N0.getNode(), DAG) || in performMulCombine()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 8413 static bool isSignExtended(SDNode *N, SelectionDAG &DAG) { in isSignExtended() function
8553 isSignExtended(N0, DAG) && isSignExtended(N1, DAG); in isAddSubSExt()
8579 bool isN0SExt = isSignExtended(N0, DAG); in LowerMUL()
8580 bool isN1SExt = isSignExtended(N1, DAG); in LowerMUL()
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| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 8719 static bool isSignExtended(SDNode *N, SelectionDAG &DAG) { in isSignExtended() function
8859 isSignExtended(N0, DAG) && isSignExtended(N1, DAG); in isAddSubSExt()
8885 bool isN0SExt = isSignExtended(N0, DAG); in LowerMUL()
8886 bool isN1SExt = isSignExtended(N1, DAG); in LowerMUL()
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