| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86InstrFragmentsSIMD.td | 1107 cast<MaskedLoadSDNode>(N)->isUnindexed();
1122 cast<MaskedLoadSDNode>(N)->isUnindexed();
1132 cast<MaskedStoreSDNode>(N)->isUnindexed();
1147 cast<MaskedStoreSDNode>(N)->isUnindexed();
1156 cast<MaskedStoreSDNode>(N)->isUnindexed();
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| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86InstrFragmentsSIMD.td | 1052 cast<MaskedLoadSDNode>(N)->isUnindexed();
1067 cast<MaskedLoadSDNode>(N)->isUnindexed();
1077 cast<MaskedStoreSDNode>(N)->isUnindexed();
1092 cast<MaskedStoreSDNode>(N)->isUnindexed();
1101 cast<MaskedStoreSDNode>(N)->isUnindexed();
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| /external/llvm-project/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLoweringHVX.cpp | 1815 assert(cast<LoadSDNode>(Op)->isUnindexed()); in SplitHvxMemOp()
1824 assert(cast<StoreSDNode>(Op)->isUnindexed()); in SplitHvxMemOp()
1834 assert(MaskN->isUnindexed()); in SplitHvxMemOp()
1873 assert(LoadN->isUnindexed() && "Not widening indexed loads yet"); in WidenHvxLoad()
1905 assert(StoreN->isUnindexed() && "Not widening indexed stores yet"); in WidenHvxStore()
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| D | HexagonISelLowering.cpp | 2899 if (!LN->isUnindexed()) in LowerUnalignedLoad()
|
| /external/llvm-project/llvm/utils/TableGen/ |
| D | CodeGenDAGPatterns.cpp | 887 if (isUnindexed()) in getPredCode()
903 if (!isUnindexed() && !isNonExtLoad() && !isAnyExtLoad() && in getPredCode()
925 if (!isUnindexed() && !isTruncStore() && !isNonTruncStore() && in getPredCode()
1050 if (isUnindexed()) in getPredCode()
1148 bool TreePredicateFn::isUnindexed() const { in isUnindexed() function in TreePredicateFn
1275 if (isUnindexed()) in getCodeToRunOnSDNode()
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| D | CodeGenDAGPatterns.h | 550 bool isUnindexed() const;
|
| D | GlobalISelEmitter.cpp | 217 if (P.isUnindexed()) in explainPredicates()
332 if (Predicate.isUnindexed()) in isTrivialOperatorNode()
3826 if (Predicate.isUnindexed()) in addBuiltinPredicates()
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| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | SelectionDAGNodes.h | 2214 bool isUnindexed() const { return getAddressingMode() == ISD::UNINDEXED; }
2318 bool isUnindexed() const { return getAddressingMode() == ISD::UNINDEXED; }
|
| /external/llvm-project/llvm/include/llvm/CodeGen/ |
| D | SelectionDAGNodes.h | 2229 bool isUnindexed() const { return getAddressingMode() == ISD::UNINDEXED; }
2330 bool isUnindexed() const { return getAddressingMode() == ISD::UNINDEXED; }
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | DAGCombiner.cpp | 3241 LN0->isUnindexed() && N0.hasOneUse() && SDValue(LN0, 0).hasOneUse()) { in visitAND()
6142 if (LN0->getExtensionType() != ISD::ZEXTLOAD && LN0->isUnindexed()) { in visitSIGN_EXTEND()
6434 if (LN0->getExtensionType() != ISD::SEXTLOAD && LN0->isUnindexed()) { in visitZERO_EXTEND()
10108 if (OptLevel != CodeGenOpt::None && LD->isUnindexed()) { in visitLOAD()
10131 if (UseAA && LD->isUnindexed()) { in visitLOAD()
12022 ST->isUnindexed()) { in visitSTORE()
12041 if (Value.isUndef() && ST->isUnindexed()) in visitSTORE()
12045 if (OptLevel != CodeGenOpt::None && ST->isUnindexed()) { in visitSTORE()
12071 if (UseAA && ST->isUnindexed()) { in visitSTORE()
12092 if (ST->isTruncatingStore() && ST->isUnindexed() && in visitSTORE()
[all …]
|
| D | LegalizeVectorTypes.cpp | 224 assert(N->isUnindexed() && "Indexed vector load?"); in ScalarizeVecRes_LOAD()
533 assert(N->isUnindexed() && "Indexed store of one-element vector?"); in ScalarizeVecOp_STORE()
1861 assert(N->isUnindexed() && "Indexed store of vector?"); in SplitVecOp_STORE()
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| D | TargetLowering.cpp | 1522 if (!Lod->isVolatile() && Lod->isUnindexed()) { in SimplifySetCC()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorTypes.cpp | 327 assert(N->isUnindexed() && "Indexed vector load?"); in ScalarizeVecRes_LOAD()
744 assert(N->isUnindexed() && "Indexed store of one-element vector?"); in ScalarizeVecOp_STORE()
1533 assert(MLD->isUnindexed() && "Indexed masked load during type legalization!"); in SplitVecRes_MLOAD()
2308 assert(N->isUnindexed() && "Indexed masked store of vector?"); in SplitVecOp_MSTORE()
2432 assert(N->isUnindexed() && "Indexed store of vector?"); in SplitVecOp_STORE()
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| D | DAGCombiner.cpp | 9696 LN00->getExtensionType() != ISD::ZEXTLOAD && LN00->isUnindexed()) { in visitSIGN_EXTEND()
10009 LN00->getExtensionType() != ISD::SEXTLOAD && LN00->isUnindexed()) { in visitZERO_EXTEND()
14358 if (OptLevel != CodeGenOpt::None && LD->isUnindexed() && !LD->isAtomic()) { in visitLOAD()
14372 if (LD->isUnindexed()) { in visitLOAD()
16388 ST->isUnindexed()) { in visitSTORE()
16406 if (Value.isUndef() && ST->isUnindexed()) in visitSTORE()
16410 if (OptLevel != CodeGenOpt::None && ST->isUnindexed() && !ST->isAtomic()) { in visitSTORE()
16433 if (ST->isUnindexed()) { in visitSTORE()
16445 if (ST->isTruncatingStore() && ST->isUnindexed() && in visitSTORE()
16479 ST->isUnindexed() && ST->isSimple() && in visitSTORE()
[all …]
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| /external/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorTypes.cpp | 340 assert(N->isUnindexed() && "Indexed vector load?"); in ScalarizeVecRes_LOAD()
759 assert(N->isUnindexed() && "Indexed store of one-element vector?"); in ScalarizeVecOp_STORE()
1654 assert(MLD->isUnindexed() && "Indexed masked load during type legalization!"); in SplitVecRes_MLOAD()
2451 assert(N->isUnindexed() && "Indexed masked store of vector?"); in SplitVecOp_MSTORE()
2591 assert(N->isUnindexed() && "Indexed store of vector?"); in SplitVecOp_STORE()
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| D | DAGCombiner.cpp | 9521 MST->isUnindexed() && !MST->isCompressingStore() && in visitMSTORE()
9578 MLD->isUnindexed() && !MLD->isExpandingLoad() && in visitMLOAD()
10592 LN00->getExtensionType() != ISD::ZEXTLOAD && LN00->isUnindexed()) { in visitSIGN_EXTEND()
10916 LN00->getExtensionType() != ISD::SEXTLOAD && LN00->isUnindexed()) { in visitZERO_EXTEND()
15385 if (OptLevel != CodeGenOpt::None && LD->isUnindexed() && !LD->isAtomic()) { in visitLOAD()
15400 if (LD->isUnindexed()) { in visitLOAD()
17490 ST->isUnindexed()) { in visitSTORE()
17508 if (Value.isUndef() && ST->isUnindexed()) in visitSTORE()
17512 if (OptLevel != CodeGenOpt::None && ST->isUnindexed() && !ST->isAtomic()) { in visitSTORE()
17536 if (ST->isUnindexed()) { in visitSTORE()
[all …]
|
| /external/llvm/include/llvm/CodeGen/ |
| D | SelectionDAGNodes.h | 1801 bool isUnindexed() const { return getAddressingMode() == ISD::UNINDEXED; }
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLoweringHVX.cpp | 1484 assert(BN->isUnindexed()); in SplitHvxMemOp()
|
| D | HexagonISelLowering.cpp | 2731 if (!LN->isUnindexed()) in LowerUnalignedLoad()
|
| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.td | 289 cast<MaskedLoadSDNode>(N)->isUnindexed() &&
298 cast<MaskedLoadSDNode>(N)->isUnindexed();
320 cast<MaskedLoadSDNode>(N)->isUnindexed();
342 cast<MaskedLoadSDNode>(N)->isUnindexed() &&
351 cast<MaskedStoreSDNode>(N)->isUnindexed() &&
359 cast<MaskedStoreSDNode>(N)->isUnindexed();
381 cast<MaskedStoreSDNode>(N)->isUnindexed() &&
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.td | 275 cast<MaskedLoadSDNode>(N)->isUnindexed() &&
284 cast<MaskedLoadSDNode>(N)->isUnindexed();
306 cast<MaskedLoadSDNode>(N)->isUnindexed();
328 cast<MaskedLoadSDNode>(N)->isUnindexed() &&
337 cast<MaskedStoreSDNode>(N)->isUnindexed() &&
345 cast<MaskedStoreSDNode>(N)->isUnindexed();
367 cast<MaskedStoreSDNode>(N)->isUnindexed() &&
|
| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 9387 assert(LD->isUnindexed() && "Expected a unindexed load"); in LowerPredicateLoad()
9413 assert(LD->isUnindexed() && "Loads should be unindexed at this point."); in LowerLOAD()
9435 assert(ST->isUnindexed() && "Expected a unindexed store"); in LowerPredicateStore()
9461 assert(ST->isUnindexed() && "Stores should be unindexed at this point."); in LowerSTORE()
13646 if (LN0->hasOneUse() && LN0->isUnindexed() && in PerformVMOVhrCombine()
14532 if (LD && Op.hasOneUse() && LD->isUnindexed() && in PerformVDUPCombine()
14649 if (!St->isSimple() || St->isTruncatingStore() || !St->isUnindexed()) in PerformSplittingToNarrowingStores()
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 8015 assert(LN->isUnindexed() && "Indexed v4i1 loads are not supported"); in LowerVectorLoad()
8104 assert(SN->isUnindexed() && "Indexed v4i1 stores are not supported"); in LowerVectorStore()
10610 if (cast<StoreSDNode>(N)->isUnindexed() && in PerformDAGCombine()
10766 if (LD->isUnindexed() && VT.isVector() && in PerformDAGCombine()
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| D | PPCISelDAGToDAG.cpp | 2886 if (LD->isUnindexed() && LD->hasOneUse() && Op1.hasOneUse() && in Select()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 10094 assert(LN->isUnindexed() && "Indexed v4i1 loads are not supported"); in LowerVectorLoad()
10181 assert(SN->isUnindexed() && "Indexed v4i1 stores are not supported"); in LowerVectorStore()
13751 if (cast<StoreSDNode>(N)->isUnindexed() && Opcode == ISD::BSWAP && in PerformDAGCombine()
13941 if (LD->isUnindexed() && VT.isVector() && in PerformDAGCombine()
|