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Searched refs:is_baytrail (Results 1 – 18 of 18) sorted by relevance

/external/mesa3d/src/mesa/drivers/dri/i965/
Dgen7_l3_state.c139 const bool urb_low_bw = has_slm && !devinfo->is_baytrail; in setup_l3_config()
143 const unsigned n0_urb = (devinfo->is_baytrail ? 32 : 0); in setup_l3_config()
152 devinfo->is_baytrail ? VLV_L3SQCREG1_SQGHPCI_DEFAULT : in setup_l3_config()
Dgen7_urb.c176 if (devinfo->gen < 8 && !devinfo->is_haswell && !devinfo->is_baytrail) in gen7_emit_push_constant_state()
254 if (devinfo->gen == 7 && !devinfo->is_haswell && !devinfo->is_baytrail) in gen7_upload_urb()
Dintel_extensions.c296 if (devinfo->gen >= 8 || devinfo->is_haswell || devinfo->is_baytrail) { in intelInitExtensions()
304 if (devinfo->gen >= 8 || devinfo->is_baytrail) { in intelInitExtensions()
Dintel_mipmap_tree.h731 return devinfo->gen < 8 && !devinfo->is_baytrail && is_etc; in intel_miptree_needs_fake_etc()
Dbrw_draw_upload.c257 devinfo->gen <= 7 && !devinfo->is_baytrail && !devinfo->is_haswell; in brw_get_vertex_surface_type()
DgenX_state_upload.c585 (GEN_GEN <= 7 && !GEN_IS_HASWELL && !devinfo->is_baytrail) * 2; in genX()
3096 if (GEN_GEN == 7 && !GEN_IS_HASWELL && !devinfo->is_baytrail &&
Dintel_mipmap_tree.c203 if (devinfo->gen >= 8 || devinfo->is_baytrail) in intel_lower_compressed_format()
/external/mesa3d/src/intel/common/
Dgen_l3_config.c168 return (devinfo->is_baytrail ? &vlv_l3_list : &ivb_l3_list); in get_l3_list()
272 w.w[GEN_L3P_RO] = devinfo->is_baytrail ? 0.5 : 1.0; in gen_get_default_l3_weights()
Dgen_decoder.c513 if (devinfo->is_baytrail || devinfo->is_haswell) { in devinfo_to_gen()
/external/mesa3d/src/intel/dev/
Dgen_device_info.h55 bool is_baytrail; member
Dgen_device_info.c272 GEN7_FEATURES, .is_baytrail = true, .gt = 1,
/external/mesa3d/src/intel/compiler/
Dbrw_nir_lower_image_load_store.c203 if (devinfo->gen < 8 && !devinfo->is_baytrail) { in image_address()
Dbrw_vec4_generator.cpp741 const bool ivb = devinfo->is_ivybridge || devinfo->is_baytrail; in generate_tcs_get_instance_id()
1061 const bool ivb = devinfo->is_ivybridge || devinfo->is_baytrail; in generate_tcs_create_barrier_header()
/external/mesa3d/src/intel/isl/
Disl_format.c716 if (devinfo->is_baytrail) { in isl_format_supports_sampling()
749 if (devinfo->is_baytrail) { in isl_format_supports_filtering()
785 if (devinfo->is_baytrail) in isl_format_supports_vertex_fetch()
Disl.h85 #define ISL_DEV_IS_BAYTRAIL(__dev) ((__dev)->info->is_baytrail)
/external/mesa3d/src/intel/vulkan/
Danv_device.c331 } else if (devinfo.gen == 7 && !devinfo.is_baytrail) { in anv_physical_device_try_create()
333 } else if (devinfo.gen == 7 && devinfo.is_baytrail) { in anv_physical_device_try_create()
929 pdevice->info.is_baytrail, in anv_GetPhysicalDeviceFeatures()
DgenX_cmd_buffer.c2002 const bool urb_low_bw = has_slm && !devinfo->is_baytrail; in genX()
2006 const unsigned n0_urb = devinfo->is_baytrail ? 32 : 0; in genX()
2017 devinfo->is_baytrail ? VLV_L3SQCREG1_SQGHPCI_DEFAULT : in genX()
DgenX_pipeline.c2332 if (!device->info.is_haswell && !device->info.is_baytrail)