1 // Copyright 2015, VIXL authors 2 // All rights reserved. 3 // 4 // Redistribution and use in source and binary forms, with or without 5 // modification, are permitted provided that the following conditions are met: 6 // 7 // * Redistributions of source code must retain the above copyright notice, 8 // this list of conditions and the following disclaimer. 9 // * Redistributions in binary form must reproduce the above copyright notice, 10 // this list of conditions and the following disclaimer in the documentation 11 // and/or other materials provided with the distribution. 12 // * Neither the name of ARM Limited nor the names of its contributors may be 13 // used to endorse or promote products derived from this software without 14 // specific prior written permission. 15 // 16 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND 17 // ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18 // WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19 // DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE 20 // FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 // DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 // SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 23 // CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 // OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 27 28 // --------------------------------------------------------------------- 29 // This file is auto generated using tools/generate_simulator_traces.py. 30 // 31 // PLEASE DO NOT EDIT. 32 // --------------------------------------------------------------------- 33 34 #ifndef VIXL_SIM_FCVTAS_WH_TRACE_AARCH64_H_ 35 #define VIXL_SIM_FCVTAS_WH_TRACE_AARCH64_H_ 36 37 const int32_t kExpected_fcvtas_wh[] = { 38 INT32_C(0), 39 INT32_C(0), 40 INT32_C(0), 41 INT32_C(1), 42 INT32_C(1), 43 INT32_C(1), 44 INT32_C(1), 45 INT32_C(1), 46 INT32_C(2), 47 INT32_C(10), 48 INT32_C(65504), 49 INT32_C(2147483647), 50 INT32_C(0), 51 INT32_C(0), 52 INT32_C(0), 53 INT32_C(0), 54 INT32_C(0), 55 INT32_C(0), 56 INT32_C(0), 57 INT32_C(0), 58 INT32_C(0), 59 INT32_C(0), 60 -INT32_C(1), 61 -INT32_C(1), 62 -INT32_C(1), 63 -INT32_C(1), 64 -INT32_C(1), 65 -INT32_C(2), 66 -INT32_C(10), 67 -INT32_C(65504), 68 -INT32_C(2147483647) - 1, 69 INT32_C(0), 70 INT32_C(0), 71 INT32_C(0), 72 INT32_C(0), 73 INT32_C(0), 74 INT32_C(0), 75 INT32_C(0), 76 INT32_C(1024), 77 INT32_C(1025), 78 INT32_C(1026), 79 INT32_C(1027), 80 INT32_C(1347), 81 INT32_C(2044), 82 INT32_C(2045), 83 INT32_C(2046), 84 INT32_C(2047), 85 INT32_C(512), 86 INT32_C(513), 87 INT32_C(513), 88 INT32_C(514), 89 INT32_C(913), 90 INT32_C(1022), 91 INT32_C(1023), 92 INT32_C(1023), 93 INT32_C(1024), 94 INT32_C(256), 95 INT32_C(256), 96 INT32_C(257), 97 INT32_C(257), 98 INT32_C(333), 99 INT32_C(511), 100 INT32_C(511), 101 INT32_C(512), 102 INT32_C(512), 103 -INT32_C(1024), 104 -INT32_C(1025), 105 -INT32_C(1026), 106 -INT32_C(1027), 107 -INT32_C(1347), 108 -INT32_C(2044), 109 -INT32_C(2045), 110 -INT32_C(2046), 111 -INT32_C(2047), 112 -INT32_C(512), 113 -INT32_C(513), 114 -INT32_C(513), 115 -INT32_C(514), 116 -INT32_C(913), 117 -INT32_C(1022), 118 -INT32_C(1023), 119 -INT32_C(1023), 120 -INT32_C(1024), 121 -INT32_C(256), 122 -INT32_C(256), 123 -INT32_C(257), 124 -INT32_C(257), 125 -INT32_C(333), 126 -INT32_C(511), 127 -INT32_C(511), 128 -INT32_C(512), 129 -INT32_C(512), 130 INT32_C(0), 131 INT32_C(0), 132 INT32_C(0), 133 INT32_C(0), 134 INT32_C(0), 135 INT32_C(0), 136 INT32_C(0), 137 INT32_C(0), 138 INT32_C(0), 139 }; 140 const unsigned kExpectedCount_fcvtas_wh = 101; 141 142 #endif // VIXL_SIM_FCVTAS_WH_TRACE_AARCH64_H_ 143