| /external/vixl/test/aarch64/ |
| D | test-assembler-sve-aarch64.cc | 543 TEST_SVE(sve_mla_mls_h) { MlaMlsHelper(config, kHRegSize); } in TEST_SVE()
1623 ASSERT_EQUAL_64(0x4000000000000000 + core.GetSVELaneCount(kHRegSize), x21); in TEST_SVE()
1734 ASSERT_EQUAL_64(core.GetSVELaneCount(kHRegSize), x22); in TEST_SVE()
1843 ASSERT_EQUAL_64(0x4000000000000000 + core.GetSVELaneCount(kHRegSize), x21); in TEST_SVE()
1978 int h_lane_count = core.GetSVELaneCount(kHRegSize); in TEST_SVE()
2126 int h_lane_count = core.GetSVELaneCount(kHRegSize); in TEST_SVE()
2286 int h_lane_count = core.GetSVELaneCount(kHRegSize); in TEST_SVE()
2343 int h_lane_count = core.GetSVELaneCount(kHRegSize); in TEST_SVE()
2348 uint64_t h_mask = GetUintMask(kHRegSize); in TEST_SVE()
3195 PnextHelper(config, kHRegSize, in0, in0, exp00); in TEST_SVE()
[all …]
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| D | test-api-aarch64.cc | 247 VIXL_CHECK(VRegister(1, kHRegSize).Is(h1)); in TEST()
254 VIXL_CHECK(VRegister(1, kHRegSize, 1).Is(h1)); in TEST()
291 VIXL_CHECK(ZRegister(1, kHRegSize).Is(z1.VnH())); in TEST()
306 VIXL_CHECK(PRegisterWithLaneSize(1, kHRegSize).Is(p1.VnH())); in TEST()
327 VIXL_CHECK(CPURegister(3, kHRegSize, CPURegister::kVRegister).Is(h3)); in TEST()
580 VIXL_CHECK(p14.VnH().GetLaneSizeInBits() == kHRegSize); in TEST()
1561 temps.Include(ZRegister(12), ZRegister(13, kHRegSize), z14); in TEST()
1593 temps.Exclude(ZRegister(12), ZRegister(13, kHRegSize), z14); in TEST()
1646 temps.Include(PRegister(11), PRegisterWithLaneSize(12, kHRegSize)); in TEST()
1678 temps.Exclude(PRegister(11), PRegisterWithLaneSize(12, kHRegSize)); in TEST()
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| D | test-utils-aarch64.h | 177 case kHRegSize: in zreg_lane()
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| D | test-utils-aarch64.cc | 736 case kHRegSize: in GetSignallingNan()
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| D | test-simulator-aarch64.cc | 243 (d_size == kHRegSize)); in Test1Op_Helper()
245 (n_size == kHRegSize)); in Test1Op_Helper()
388 (reg_size == kHRegSize)); in Test2Op_Helper()
545 (reg_size == kHRegSize)); in Test3Op_Helper()
974 (n_size == kHRegSize)); in TestFPToFixed_Helper()
1040 (n_size == kHRegSize)); in TestFPToInt_Helper()
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| /external/vixl/benchmarks/aarch64/ |
| D | bench-utils.cc | 92 if (entropy == 0) return kHRegSize; in PickFPSize()
363 if (other_size < kHRegSize) other_size = kDRegSize; in GenerateFPSequence()
364 if (other_size > kDRegSize) other_size = kHRegSize; in GenerateFPSequence()
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| D | bench-utils.h | 238 vixl::aarch64::VRegister PickH() { return PickV(vixl::aarch64::kHRegSize); } in PickH()
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| /external/vixl/src/aarch64/ |
| D | registers-aarch64.h | 441 case kHRegSize: in EncodeSizeInBits()
613 ZRegister VnH() const { return ZRegister(GetCode(), kHRegSize); } in VnH()
744 return PRegisterWithLaneSize(GetCode(), kHRegSize); in VnH()
773 V(HRegister, kHRegSize, VRegister) \
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| D | logic-aarch64.cc | 2709 case kHRegSize: in fadda()
2766 if (LaneSizeInBitsFromFormat(vform) == kHRegSize) { in fcadd()
2845 if (LaneSizeInBitsFromFormat(vform) == kHRegSize) { in fcmla()
2862 if (LaneSizeInBitsFromFormat(vform) == kHRegSize) { in fcmla()
4828 if (LaneSizeInBitsFromFormat(vform) == kHRegSize) { \
4872 if (LaneSizeInBitsFromFormat(vform) == kHRegSize) { in frecps()
4904 if (LaneSizeInBitsFromFormat(vform) == kHRegSize) { in frsqrts()
4973 if (LaneSizeInBitsFromFormat(vform) == kHRegSize) { in fcmp()
4990 if (LaneSizeInBitsFromFormat(vform) == kHRegSize) { in fcmp_zero()
5012 if (LaneSizeInBitsFromFormat(vform) == kHRegSize) { in fabscmp()
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| D | macro-assembler-sve-aarch64.cc | 387 if (zd.GetLaneSizeInBits() >= kHRegSize) { in Cpy()
390 case kHRegSize: in Cpy()
764 case kHRegSize: in Fdup()
785 case kHRegSize: in Fdup()
806 case kHRegSize: in Fdup()
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| D | instructions-aarch64.h | 55 const unsigned kHRegSize = 16; variable
57 const unsigned kHRegSizeInBytes = kHRegSize / 8;
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| D | instructions-aarch64.cc | 38 VIXL_ASSERT((reg_size == kBRegSize) || (reg_size == kHRegSize) || in RepeatBitsAcrossReg()
1233 return kHRegSize; in RegisterSizeInBitsFromFormat()
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| D | simulator-aarch64.cc | 488 VIXL_ASSERT((reg_size == kBRegSize) || (reg_size == kHRegSize) || in ShiftOperand()
979 case kHRegSize: in PrintVRegister()
8384 dst_data_size = kHRegSize; in VisitSVEFPConvertToInt()
8385 src_data_size = kHRegSize; in VisitSVEFPConvertToInt()
8390 src_data_size = kHRegSize; in VisitSVEFPConvertToInt()
8395 src_data_size = kHRegSize; in VisitSVEFPConvertToInt()
8433 dst_data_size = kHRegSize; in VisitSVEFPConvertPrecision()
8442 src_data_size = kHRegSize; in VisitSVEFPConvertPrecision()
8446 src_data_size = kHRegSize; in VisitSVEFPConvertPrecision()
8453 dst_data_size = kHRegSize; in VisitSVEFPConvertPrecision()
[all …]
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| D | assembler-sve-aarch64.cc | 4488 case kHRegSize: in SVEGatherPrefetchVectorPlusImmediateHelper()
4523 case kHRegSize: in SVEGatherPrefetchScalarPlusImmediateHelper()
4554 case kHRegSize: in SVEContiguousPrefetchScalarPlusScalarHelper()
4594 case kHRegSize: in SVEContiguousPrefetchScalarPlusVectorHelper()
4618 case kHRegSize: in SVEContiguousPrefetchScalarPlusVectorHelper()
4643 case kHRegSize: in SVEContiguousPrefetchScalarPlusVectorHelper()
4716 SVEPrefetchHelper(prfop, pg, addr, kHRegSize); in prfh()
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| D | assembler-aarch64.cc | 5883 VIXL_ASSERT((width == kBRegSize) || (width == kHRegSize) || in IsImmLogical()
6089 case kHRegSize: in LoadOpFor()
6112 case kHRegSize: in StoreOpFor()
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| D | disasm-aarch64.cc | 9540 case kHRegSize: in AppendRegisterNameToOutput()
9885 reg_size = kHRegSize; in SubstituteRegisterField()
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