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Searched refs:lane0 (Results 1 – 11 of 11) sorted by relevance

/external/llvm-project/llvm/test/CodeGen/AArch64/
Darm64-addp.ll7 %lane0.i = extractelement <2 x double> %a, i32 0
9 %vpaddd.i = fadd double %lane0.i, %lane1.i
18 %lane0.i = extractelement <2 x i64> %a, i32 0
20 %vpaddd.i = add i64 %lane0.i, %lane1.i
28 %lane0.i = extractelement <2 x float> %a, i32 0
30 %vpaddd.i = fadd float %lane0.i, %lane1.i
/external/llvm/test/CodeGen/AArch64/
Darm64-addp.ll7 %lane0.i = extractelement <2 x double> %a, i32 0
9 %vpaddd.i = fadd double %lane0.i, %lane1.i
18 %lane0.i = extractelement <2 x i64> %a, i32 0
20 %vpaddd.i = add i64 %lane0.i, %lane1.i
28 %lane0.i = extractelement <2 x float> %a, i32 0
30 %vpaddd.i = fadd float %lane0.i, %lane1.i
/external/eigen/Eigen/src/Core/arch/AVX512/
DPacketMath.h464 Packet8f lane0 = _mm256_broadcast_ps((const __m128*)(const void*)from);
466 lane0 = _mm256_blend_ps(
467 lane0, _mm256_castps128_ps256(_mm_permute_ps(
468 _mm256_castps256_ps128(lane0), _MM_SHUFFLE(1, 0, 1, 0))),
472 lane0 = _mm256_permute_ps(lane0, _MM_SHUFFLE(3, 3, 2, 2));
486 return _mm512_insertf32x8(res, lane0, 0);
491 res = _mm512_insertf32x4(res, _mm256_extractf128_ps(lane0, 0), 0);
492 res = _mm512_insertf32x4(res, _mm256_extractf128_ps(lane0, 1), 1);
502 Packet4d lane0 = _mm256_broadcast_pd((const __m128d*)(const void*)from);
503 lane0 = _mm256_permute_pd(lane0, 3 << 2);
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/external/tensorflow/third_party/eigen3/unsupported/Eigen/CXX11/src/FixedPoint/
DPacketMathAVX512.h402 Packet4i lane0 = _mm512_extracti32x4_epi32(a.m_val, 0);
407 _mm_min_epi32(_mm_min_epi32(lane0, lane1), _mm_min_epi32(lane2, lane3));
414 Packet4i lane0 = _mm512_extracti32x4_epi32(a.m_val, 0);
419 _mm_max_epi32(_mm_max_epi32(lane0, lane1), _mm_max_epi32(lane2, lane3));
426 Packet4i lane0 = _mm512_extracti32x4_epi32(a.m_val, 0);
431 _mm_min_epi16(_mm_min_epi16(lane0, lane1), _mm_min_epi16(lane2, lane3));
440 Packet4i lane0 = _mm512_extracti32x4_epi32(a.m_val, 0);
445 _mm_max_epi16(_mm_max_epi16(lane0, lane1), _mm_max_epi16(lane2, lane3));
454 Packet4i lane0 = _mm512_extracti32x4_epi32(a.m_val, 0);
459 _mm_min_epu8(_mm_min_epu8(lane0, lane1), _mm_min_epu8(lane2, lane3));
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/external/mesa3d/prebuilt-intermediates/bifrost/
Dbi_generated_pack.h234 unsigned lane0 = lane0_temp; in pan_pack_add_fatan_table_f16() local
235 assert(lane0 < 2); in pan_pack_add_fatan_table_f16()
237 return 0x67900 | (src0 << 0) | (src1 << 3) | (lane1 << 6) | (lane0 << 7); in pan_pack_add_fatan_table_f16()
569 unsigned lane0 = lane0_temp; in pan_pack_add_branchc_i16() local
570 assert(lane0 < 2); in pan_pack_add_branchc_i16()
573 if (lane0 == 0) derived_9 = 0; in pan_pack_add_branchc_i16()
574 else if (lane0 == 1) derived_9 = 1; in pan_pack_add_branchc_i16()
578 if (lane0 == 1) derived_3 = 0; in pan_pack_add_branchc_i16()
579 else if (lane0 == 0) derived_3 = 1; in pan_pack_add_branchc_i16()
1031 unsigned lane0 = lane0_temp; in pan_pack_add_mkvec_v2i16() local
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Dbifrost_gen_disasm.c66 const char *lane0 = lane0_table[_BITS(bits, 8, 1)]; in bi_disasm_add_frcp_f16() local
77 fputs(lane0, fp); in bi_disasm_add_frcp_f16()
835 const char *lane0 = lane0_table[_BITS(bits, 4, 2)]; in bi_disasm_add_u8_to_u32() local
842 fputs(lane0, fp); in bi_disasm_add_u8_to_u32()
984 const char *lane0 = lane0_table[_BITS(bits, 4, 1)]; in bi_disasm_add_u16_to_f32() local
991 fputs(lane0, fp); in bi_disasm_add_u16_to_f32()
1126 const char *lane0 = lane0_table[_BITS(bits, 4, 2)]; in bi_disasm_add_s8_to_f32() local
1133 fputs(lane0, fp); in bi_disasm_add_s8_to_f32()
1299 const char *lane0 = lane0_table[_BITS(bits, 12, 1)]; in bi_disasm_fma_mkvec_v4i8() local
1325 fputs(lane0, fp); in bi_disasm_fma_mkvec_v4i8()
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/external/libvpx/libvpx/vp9/common/arm/neon/
Dvp9_highbd_iht16x16_add_neon.c72 #define highbd_iadst_butterfly(in0, in1, c, lane0, lane1, s0, s1) \ argument
74 vmull_lane_s32_dual(in0, c, lane0, s0); \
77 vmlsl_lane_s32_dual(in1, c, lane0, s1); \
/external/vixl/test/aarch64/
Dtest-assembler-sve-aarch64.cc7404 uint8_t lane0 = 1 - (3 * i); in TEST_SVE() local
7406 MemoryWrite(middle, 0, (i * reg_count) + 0, lane0); in TEST_SVE()
7414 uint16_t lane0 = -2 + (5 * i); in TEST_SVE() local
7416 MemoryWrite(middle, offset, (i * reg_count) + 0, lane0); in TEST_SVE()
7424 uint32_t lane0 = 3 - (7 * i); in TEST_SVE() local
7426 MemoryWrite(middle, offset, (i * reg_count) + 0, lane0); in TEST_SVE()
7434 uint64_t lane0 = -7 + (3 * i); in TEST_SVE() local
7436 MemoryWrite(middle, offset, (i * reg_count) + 0, lane0); in TEST_SVE()
7575 uint8_t lane0 = -4 + (11 * i); in TEST_SVE() local
7577 MemoryWrite(middle, 0, (i * reg_count) + 0, lane0); in TEST_SVE()
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/external/mesa3d/src/amd/llvm/
Dac_llvm_build.h532 LLVMValueRef ac_build_quad_swizzle(struct ac_llvm_context *ctx, LLVMValueRef src, unsigned lane0,
Dac_llvm_build.c3416 static inline enum dpp_ctrl dpp_quad_perm(unsigned lane0, unsigned lane1, unsigned lane2, in dpp_quad_perm() argument
3419 assert(lane0 < 4 && lane1 < 4 && lane2 < 4 && lane3 < 4); in dpp_quad_perm()
3420 return _dpp_quad_perm | lane0 | (lane1 << 2) | (lane2 << 4) | (lane3 << 6); in dpp_quad_perm()
4261 LLVMValueRef ac_build_quad_swizzle(struct ac_llvm_context *ctx, LLVMValueRef src, unsigned lane0, in ac_build_quad_swizzle() argument
4264 unsigned mask = dpp_quad_perm(lane0, lane1, lane2, lane3); in ac_build_quad_swizzle()
/external/llvm-project/llvm/test/Transforms/InstCombine/AMDGPU/
Damdgcn-intrinsics.ll2627 define i32 @readlane_idempotent_different_lanes(i32 %arg, i32 %lane0, i32 %lane1) {
2633 %read0 = call i32 @llvm.amdgcn.readlane(i32 %arg, i32 %lane0)