| /external/tensorflow/third_party/eigen3/unsupported/Eigen/CXX11/src/FixedPoint/ |
| D | PacketMathAVX512.h | 405 Packet4i lane3 = _mm512_extracti32x4_epi32(a.m_val, 3);
407 _mm_min_epi32(_mm_min_epi32(lane0, lane1), _mm_min_epi32(lane2, lane3));
417 Packet4i lane3 = _mm512_extracti32x4_epi32(a.m_val, 3);
419 _mm_max_epi32(_mm_max_epi32(lane0, lane1), _mm_max_epi32(lane2, lane3));
429 Packet4i lane3 = _mm512_extracti32x4_epi32(a.m_val, 3);
431 _mm_min_epi16(_mm_min_epi16(lane0, lane1), _mm_min_epi16(lane2, lane3));
443 Packet4i lane3 = _mm512_extracti32x4_epi32(a.m_val, 3);
445 _mm_max_epi16(_mm_max_epi16(lane0, lane1), _mm_max_epi16(lane2, lane3));
457 Packet4i lane3 = _mm512_extracti32x4_epi32(a.m_val, 3);
459 _mm_min_epu8(_mm_min_epu8(lane0, lane1), _mm_min_epu8(lane2, lane3));
[all …]
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| /external/eigen/Eigen/src/Core/arch/AVX512/ |
| D | PacketMath.h | 891 Packet4f lane3 = _mm512_extractf32x4_ps(a, 3);
892 Packet4f sum = padd(padd(lane0, lane1), padd(lane2, lane3));
917 Packet4f lane3 = _mm512_extractf32x4_ps(a, 3);
919 Packet4f sum1 = padd(lane1, lane3);
945 Packet4f lane3 = _mm512_extractf32x4_ps(a, 3);
946 Packet4f res = pmul(pmul(lane0, lane1), pmul(lane2, lane3));
965 Packet4f lane3 = _mm512_extractf32x4_ps(a, 3);
966 Packet4f res = _mm_min_ps(_mm_min_ps(lane0, lane1), _mm_min_ps(lane2, lane3));
984 Packet4f lane3 = _mm512_extractf32x4_ps(a, 3);
985 Packet4f res = _mm_max_ps(_mm_max_ps(lane0, lane1), _mm_max_ps(lane2, lane3));
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| /external/llvm-project/llvm/test/CodeGen/ARM/ |
| D | vzip.ll | 380 …%lane3 = shufflevector <8 x i8> %3, <8 x i8> undef, <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 und…
381 …%vzip.i = shufflevector <8 x i8> %lane, <8 x i8> %lane3, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i3…
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| /external/mesa3d/src/amd/llvm/ |
| D | ac_llvm_build.h | 533 unsigned lane1, unsigned lane2, unsigned lane3);
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| D | ac_llvm_build.c | 3417 unsigned lane3) in dpp_quad_perm() argument
3419 assert(lane0 < 4 && lane1 < 4 && lane2 < 4 && lane3 < 4); in dpp_quad_perm()
3420 return _dpp_quad_perm | lane0 | (lane1 << 2) | (lane2 << 4) | (lane3 << 6); in dpp_quad_perm()
4262 unsigned lane1, unsigned lane2, unsigned lane3) in ac_build_quad_swizzle() argument
4264 unsigned mask = dpp_quad_perm(lane0, lane1, lane2, lane3); in ac_build_quad_swizzle()
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| /external/vixl/test/aarch64/ |
| D | test-assembler-sve-aarch64.cc | 8226 uint8_t lane3 = 4 - (7 * i); in TEST_SVE() local
8230 MemoryWrite(middle, 0, (i * reg_count) + 3, lane3); in TEST_SVE()
8240 uint16_t lane3 = -5 + (5 * i); in TEST_SVE() local
8244 MemoryWrite(middle, offset, (i * reg_count) + 3, lane3); in TEST_SVE()
8254 uint32_t lane3 = 5 - (7 * i); in TEST_SVE() local
8258 MemoryWrite(middle, offset, (i * reg_count) + 3, lane3); in TEST_SVE()
8268 uint64_t lane3 = -10 + (8 * i); in TEST_SVE() local
8272 MemoryWrite(middle, offset, (i * reg_count) + 3, lane3); in TEST_SVE()
8486 uint8_t lane3 = -7 + (11 * i); in TEST_SVE() local
8490 MemoryWrite(middle, offset, (i * reg_count) + 3, lane3); in TEST_SVE()
[all …]
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| /external/mesa3d/prebuilt-intermediates/bifrost/ |
| D | bi_generated_pack.h | 5640 unsigned lane3 = lane3_temp; in pan_pack_fma_mkvec_v4i8() local
5641 assert(lane3 < 2); in pan_pack_fma_mkvec_v4i8()
5643 … << 3) | (src2 << 6) | (src3 << 9) | (lane0 << 12) | (lane1 << 13) | (lane2 << 14) | (lane3 << 15); in pan_pack_fma_mkvec_v4i8()
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| D | bifrost_gen_disasm.c | 1317 const char *lane3 = lane3_table[_BITS(bits, 15, 1)]; in bi_disasm_fma_mkvec_v4i8() local
1335 fputs(lane3, fp); in bi_disasm_fma_mkvec_v4i8()
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| /external/llvm-project/llvm/test/CodeGen/X86/ |
| D | vector-shuffle-128-v16.ll | 2490 …%lane3 = shufflevector <16 x i8> %3, <16 x i8> undef, <16 x i32> <i32 0, i32 0, i32 0, i32 0, i32 …
2491 …%vzip.i = shufflevector <16 x i8> %lane, <16 x i8> %lane3, <16 x i32> <i32 0, i32 16, i32 1, i32 1…
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