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Searched refs:laneid (Results 1 – 22 of 22) sorted by relevance

/external/llvm-project/llvm/test/Analysis/DivergenceAnalysis/NVPTX/
Ddiverge.ll96 ; } while (i < laneid);
103 %laneid = call i32 @llvm.nvvm.read.ptx.sreg.laneid()
109 %exit_cond = icmp sge i32 %i1, %laneid
168 declare i32 @llvm.nvvm.read.ptx.sreg.laneid()
Ddaorder.ll44 declare i32 @llvm.nvvm.read.ptx.sreg.laneid()
Dirreducible.ll52 declare i32 @llvm.nvvm.read.ptx.sreg.laneid()
/external/llvm-project/llvm/test/Analysis/LegacyDivergenceAnalysis/NVPTX/
Ddiverge.ll96 ; } while (i < laneid);
103 %laneid = call i32 @llvm.nvvm.read.ptx.sreg.laneid()
109 %exit_cond = icmp sge i32 %i1, %laneid
211 declare i32 @llvm.nvvm.read.ptx.sreg.laneid()
/external/llvm/test/Analysis/DivergenceAnalysis/NVPTX/
Ddiverge.ll96 ; } while (i < laneid);
103 %laneid = call i32 @llvm.nvvm.read.ptx.sreg.laneid()
109 %exit_cond = icmp sge i32 %i1, %laneid
211 declare i32 @llvm.nvvm.read.ptx.sreg.laneid()
/external/llvm-project/mlir/test/Target/
Dnvvmir.mlir30 // CHECK: call i32 @llvm.nvvm.read.ptx.sreg.laneid()
31 %14 = nvvm.read.ptx.sreg.laneid : !llvm.i32
/external/llvm/test/CodeGen/NVPTX/
Dintrinsic-old.ll72 ; CHECK: mov.u32 %r{{[0-9]+}}, %laneid;
73 ; RANGE: call i32 @llvm.nvvm.read.ptx.sreg.laneid(), !range ![[LANEID:[0-9]+]]
75 %x = call i32 @llvm.nvvm.read.ptx.sreg.laneid()
281 declare i32 @llvm.nvvm.read.ptx.sreg.laneid()
/external/llvm-project/llvm/test/CodeGen/NVPTX/
Dintrinsic-old.ll72 ; CHECK: mov.u32 %r{{[0-9]+}}, %laneid;
73 ; RANGE: call i32 @llvm.nvvm.read.ptx.sreg.laneid(), !range ![[LANEID:[0-9]+]]
75 %x = call i32 @llvm.nvvm.read.ptx.sreg.laneid()
288 declare i32 @llvm.nvvm.read.ptx.sreg.laneid()
/external/llvm-project/mlir/include/mlir/Dialect/LLVMIR/
DNVVMOps.td61 def NVVM_LaneIdOp : NVVM_SpecialRegisterOp<"read.ptx.sreg.laneid">;
/external/mesa3d/src/gallium/drivers/nouveau/codegen/
Dnv50_ir_lowering_nvc0.cpp2812 Value *laneid = bld.getSSA(); in readTessCoord() local
2815 bld.mkOp1(OP_RDSV, TYPE_U32, laneid, bld.mkSysVal(SV_LANEID, 0)); in readTessCoord()
2834 bld.mkFetch(x, TYPE_F32, FILE_SHADER_OUTPUT, 0x2f0, NULL, laneid); in readTessCoord()
2836 bld.mkFetch(y, TYPE_F32, FILE_SHADER_OUTPUT, 0x2f4, NULL, laneid); in readTessCoord()
/external/llvm/include/llvm/IR/
DIntrinsicsNVVM.td3659 def int_nvvm_read_ptx_sreg_laneid : PTXReadSRegIntrinsic_r32<"laneid">;
/external/llvm-project/llvm/include/llvm/IR/
DIntrinsicsNVVM.td3965 def int_nvvm_read_ptx_sreg_laneid : PTXReadSRegIntrinsic_r32<"laneid">;
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/IR/
DIntrinsicsNVVM.td3972 def int_nvvm_read_ptx_sreg_laneid : PTXReadSRegIntrinsic_r32<"laneid">;
/external/llvm/lib/Target/NVPTX/
DNVPTXIntrinsics.td7008 PTX_READ_SREG_R32<"laneid", int_nvvm_read_ptx_sreg_laneid>;
/external/llvm-project/llvm/lib/Target/NVPTX/
DNVPTXIntrinsics.td7288 PTX_READ_SREG_R32<"laneid", int_nvvm_read_ptx_sreg_laneid>;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/NVPTX/
DNVPTXIntrinsics.td7288 PTX_READ_SREG_R32<"laneid", int_nvvm_read_ptx_sreg_laneid>;
/external/swiftshader/third_party/llvm-subzero/build/Android/include/llvm/IR/
DIntrinsics.gen3151 nvvm_read_ptx_sreg_laneid, // llvm.nvvm.read.ptx.sreg.laneid
9209 "llvm.nvvm.read.ptx.sreg.laneid",
17149 1, // llvm.nvvm.read.ptx.sreg.laneid
/external/swiftshader/third_party/llvm-subzero/build/Linux/include/llvm/IR/
DIntrinsics.gen3151 nvvm_read_ptx_sreg_laneid, // llvm.nvvm.read.ptx.sreg.laneid
9209 "llvm.nvvm.read.ptx.sreg.laneid",
17149 1, // llvm.nvvm.read.ptx.sreg.laneid
/external/swiftshader/third_party/llvm-subzero/build/Windows/include/llvm/IR/
DIntrinsics.gen3151 nvvm_read_ptx_sreg_laneid, // llvm.nvvm.read.ptx.sreg.laneid
9209 "llvm.nvvm.read.ptx.sreg.laneid",
17149 1, // llvm.nvvm.read.ptx.sreg.laneid
/external/swiftshader/third_party/llvm-subzero/build/Fuchsia/include/llvm/IR/
DIntrinsics.gen3151 nvvm_read_ptx_sreg_laneid, // llvm.nvvm.read.ptx.sreg.laneid
9209 "llvm.nvvm.read.ptx.sreg.laneid",
17149 1, // llvm.nvvm.read.ptx.sreg.laneid
/external/swiftshader/third_party/llvm-subzero/build/MacOS/include/llvm/IR/
DIntrinsics.gen3145 nvvm_read_ptx_sreg_laneid, // llvm.nvvm.read.ptx.sreg.laneid
9169 "llvm.nvvm.read.ptx.sreg.laneid",
17054 1, // llvm.nvvm.read.ptx.sreg.laneid
/external/swiftshader/third_party/llvm-10.0/configs/common/include/llvm/IR/
DIntrinsicImpl.inc4636 "llvm.nvvm.read.ptx.sreg.laneid",
14769 1, // llvm.nvvm.read.ptx.sreg.laneid