| /external/ethtool/ |
| D | sff-common.c | 42 unsigned int last_reg, const char *name) in sff_show_ascii() argument
47 while (first_reg <= last_reg && id[last_reg] == ' ') in sff_show_ascii()
48 last_reg--; in sff_show_ascii()
49 for (reg = first_reg; reg <= last_reg; reg++) { in sff_show_ascii()
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| D | sfpid.c | 279 unsigned int last_reg, const char *name) in sff8079_show_ascii() argument
284 while (first_reg <= last_reg && id[last_reg] == ' ') in sff8079_show_ascii()
285 last_reg--; in sff8079_show_ascii()
286 for (reg = first_reg; reg <= last_reg; reg++) { in sff8079_show_ascii()
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| D | sff-common.h | 181 unsigned int last_reg, const char *name);
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| /external/mesa3d/src/gallium/drivers/etnaviv/ |
| D | etnaviv_emit.h | 38 uint32_t last_reg; member
148 coalesce->last_reg = 0; in etna_coalesce_start()
176 if (coalesce->last_reg != 0) { in check_coalsence()
177 if (((coalesce->last_reg + 4) != reg) || (coalesce->last_fixp != fixp)) { in check_coalsence()
187 coalesce->last_reg = reg; in check_coalsence()
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| /external/mesa3d/src/freedreno/ir3/ |
| D | ir3_validate.c | 78 struct ir3_register *last_reg = NULL; in validate_instr() local
107 validate_assert(ctx, (last_reg->flags & IR3_REG_HALF) == (reg->flags & IR3_REG_HALF)); in validate_instr()
110 last_reg = reg; in validate_instr()
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| /external/mesa3d/src/gallium/drivers/radeonsi/ |
| D | si_pm4.c | 82 if (opcode != state->last_opcode || reg != (state->last_reg + 1)) { in si_pm4_set_reg()
87 state->last_reg = reg; in si_pm4_set_reg()
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| D | si_pm4.h | 45 unsigned last_reg; member
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIRegisterInfo.td | 42 class RegSeqNames<int last_reg, int stride, int size, string prefix,
47 !if(!le(end_reg, last_reg),
49 RegSeqNames<last_reg, stride, size, prefix, next>.ret),
54 class RegSeqDags<RegisterClass RC, int last_reg, int stride, int size,
58 !add(!add(last_reg, 2), !mul(size, -1)),
59 !add(last_reg, 1)));
63 RegSeqDags<RC, last_reg, stride, size, !add(start, 1)>.ret),
68 int last_reg, int stride, int size, string prefix> :
70 RegSeqDags<RC, last_reg, stride, size>.ret,
71 RegSeqNames<last_reg, stride, size, prefix>.ret>;
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| /external/vixl/src/aarch64/ |
| D | operands-aarch64.h | 61 unsigned last_reg) in CPURegList() argument
64 ((type == CPURegister::kRegister) && (last_reg < kNumberOfRegisters)) || in CPURegList()
66 (last_reg < kNumberOfVRegisters))); in CPURegList()
67 VIXL_ASSERT(last_reg >= first_reg); in CPURegList()
68 list_ = (UINT64_C(1) << (last_reg + 1)) - 1; in CPURegList()
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| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | SIRegisterInfo.td | 87 class RegSeqNames<int last_reg, int stride, int size, string prefix,
92 !if(!le(end_reg, last_reg),
94 RegSeqNames<last_reg, stride, size, prefix, next>.ret),
99 class RegSeqDags<RegisterClass RC, int last_reg, int stride, int size,
103 !sub(!add(last_reg, 2), size),
104 !add(last_reg, 1)));
108 RegSeqDags<RC, last_reg, stride, size, !add(start, 1)>.ret),
113 int last_reg, int stride, int size, string prefix> :
115 RegSeqDags<RC, last_reg, stride, size>.ret,
116 RegSeqNames<last_reg, stride, size, prefix>.ret>;
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| /external/kernel-headers/original/uapi/linux/ |
| D | bcache.h | 392 __u32 last_reg; member
440 __u32 last_reg; member
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| /external/mesa3d/src/intel/compiler/ |
| D | brw_vec4.cpp | 404 unsigned last_reg = ~0u, last_offset = ~0u; in opt_vector_float() local
437 last_reg = ~0u; in opt_vector_float()
444 if (last_reg != inst->dst.nr || in opt_vector_float()
465 last_reg = ~0u;; in opt_vector_float()
488 last_reg = inst->dst.nr; in opt_vector_float()
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