Searched refs:layer_ctrl (Results 1 – 5 of 5) sorted by relevance
/external/mesa3d/src/gallium/drivers/radeon/ |
D | radeon_uvd_enc_1_1.c | 243 enc->enc_pic.layer_ctrl.max_num_temporal_layers = 1; in radeon_uvd_enc_layer_control() 244 enc->enc_pic.layer_ctrl.num_temporal_layers = 1; in radeon_uvd_enc_layer_control() 247 RADEON_ENC_CS(enc->enc_pic.layer_ctrl.max_num_temporal_layers); in radeon_uvd_enc_layer_control() 248 RADEON_ENC_CS(enc->enc_pic.layer_ctrl.num_temporal_layers); in radeon_uvd_enc_layer_control() 404 radeon_uvd_enc_code_fixed_bits(enc, enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1, 3); in radeon_uvd_enc_nalu_sps_hevc() 414 for (i = 0; i < (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1); i++) in radeon_uvd_enc_nalu_sps_hevc() 417 if ((enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1) > 0) { in radeon_uvd_enc_nalu_sps_hevc() 418 for (i = (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1); i < 8; i++) in radeon_uvd_enc_nalu_sps_hevc() 562 radeon_uvd_enc_code_fixed_bits(enc, enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1, 3); in radeon_uvd_enc_nalu_vps_hevc() 573 for (i = 0; i < (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1); i++) in radeon_uvd_enc_nalu_vps_hevc() [all …]
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D | radeon_vcn_enc_1_2.c | 138 enc->enc_pic.layer_ctrl.max_num_temporal_layers = 1; in radeon_enc_layer_control() 139 enc->enc_pic.layer_ctrl.num_temporal_layers = 1; in radeon_enc_layer_control() 142 RADEON_ENC_CS(enc->enc_pic.layer_ctrl.max_num_temporal_layers); in radeon_enc_layer_control() 143 RADEON_ENC_CS(enc->enc_pic.layer_ctrl.num_temporal_layers); in radeon_enc_layer_control() 315 radeon_enc_code_fixed_bits(enc, enc->enc_pic.layer_ctrl.max_num_temporal_layers > 1 ? 0x1 : 0x0, in radeon_enc_nalu_sps() 377 radeon_enc_code_fixed_bits(enc, enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1, 3); in radeon_enc_nalu_sps_hevc() 387 for (i = 0; i < (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1); i++) in radeon_enc_nalu_sps_hevc() 390 if ((enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1) > 0) { in radeon_enc_nalu_sps_hevc() 391 for (i = (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1); i < 8; i++) in radeon_enc_nalu_sps_hevc() 564 radeon_enc_code_fixed_bits(enc, enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1, 3); in radeon_enc_nalu_vps() [all …]
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D | radeon_vcn_enc_2_0.c | 118 radeon_enc_code_fixed_bits(enc, enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1, 3); in radeon_enc_nalu_sps_hevc() 133 for (i = 0; i < (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1); i++) in radeon_enc_nalu_sps_hevc() 136 if ((enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1) > 0) { in radeon_enc_nalu_sps_hevc() 137 for (i = (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1); i < 8; i++) in radeon_enc_nalu_sps_hevc()
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D | radeon_uvd_enc.h | 371 ruvd_enc_layer_control_t layer_ctrl; member
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D | radeon_vcn_enc.h | 450 rvcn_enc_layer_control_t layer_ctrl; member
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