Searched refs:layer_regid (Results 1 – 2 of 2) sorted by relevance
| /external/mesa3d/src/gallium/drivers/freedreno/a6xx/ |
| D | fd6_program.c | 322 uint32_t vertex_regid, instance_regid, layer_regid, primitive_regid; in setup_stateobj() local
382 layer_regid = ir3_find_output_regid(gs, VARYING_SLOT_LAYER); in setup_stateobj()
386 layer_regid = regid(63, 0); in setup_stateobj()
509 if (VALIDREG(layer_regid)) { in setup_stateobj()
511 ir3_link_add(&l, layer_regid, 0x1, l.max_loc); in setup_stateobj()
816 OUT_RING(ring, CONDREG(layer_regid, A6XX_GRAS_GS_LAYER_CNTL_WRITES_LAYER)); in setup_stateobj()
827 CONDREG(layer_regid, A6XX_PC_GS_OUT_CNTL_LAYER) | in setup_stateobj()
|
| /external/mesa3d/src/freedreno/vulkan/ |
| D | tu_pipeline.c | 855 const uint32_t layer_regid = in tu6_emit_vpc() local
870 if (layer_regid != regid(63, 0)) { in tu6_emit_vpc()
872 ir3_link_add(&linkage, layer_regid, 0x1, linkage.max_loc); in tu6_emit_vpc()
960 CONDREG(layer_regid, A6XX_PC_VS_OUT_CNTL_LAYER) | in tu6_emit_vpc()
974 tu_cs_emit(cs, CONDREG(layer_regid, A6XX_GRAS_GS_LAYER_CNTL_WRITES_LAYER) | in tu6_emit_vpc()
|