/external/llvm-project/llvm/test/tools/llvm-mca/AArch64/Exynos/ |
D | asimd-ld2.s | 7 ld2r {v0.2s, v1.2s}, [sp] label 11 ld2r {v0.2d, v1.2d}, [sp] label 15 ld2r {v0.2s, v1.2s}, [sp], #8 label 19 ld2r {v0.2d, v1.2d}, [sp], #16 label 23 ld2r {v0.2s, v1.2s}, [sp], x0 label 27 ld2r {v0.2d, v1.2d}, [sp], x0 label 64 # M3-NEXT: 2 5 1.00 * ld2r { v0.2s, v1.2s }, [sp] 67 # M3-NEXT: 2 5 1.00 * ld2r { v0.2d, v1.2d }, [sp] 70 # M3-NEXT: 3 5 1.00 * ld2r { v0.2s, v1.2s }, [sp], #8 73 # M3-NEXT: 3 5 1.00 * ld2r { v0.2d, v1.2d }, [sp], #16 [all …]
|
/external/capstone/suite/MC/AArch64/ |
D | neon-simd-ldst-one-elem.s.cs | 10 0x00,0xc0,0x60,0x4d = ld2r {v0.16b, v1.16b}, [x0] 11 0xef,0xc5,0x60,0x4d = ld2r {v15.8h, v16.8h}, [x15] 12 0xff,0xcb,0x60,0x4d = ld2r {v31.4s, v0.4s}, [sp] 13 0x00,0xcc,0x60,0x4d = ld2r {v0.2d, v1.2d}, [x0] 14 0x00,0xc0,0x60,0x0d = ld2r {v0.8b, v1.8b}, [x0] 15 0xef,0xc5,0x60,0x0d = ld2r {v15.4h, v16.4h}, [x15] 16 0xff,0xcb,0x60,0x0d = ld2r {v31.2s, v0.2s}, [sp] 17 0xff,0xcf,0x60,0x0d = ld2r {v31.1d, v0.1d}, [sp] 74 0x00,0xc0,0xff,0x4d = ld2r {v0.16b, v1.16b}, [x0], #2 75 0xef,0xc5,0xff,0x4d = ld2r {v15.8h, v16.8h}, [x15], #4 [all …]
|
/external/llvm-project/llvm/test/MC/AArch64/ |
D | neon-simd-ldst-one-elem.s | 29 ld2r { v0.16b, v1.16b }, [x0] 30 ld2r { v15.8h, v16.8h }, [x15] 31 ld2r { v31.4s, v0.4s }, [sp] 32 ld2r { v0.2d, v1.2d }, [x0] 33 ld2r { v0.8b, v1.8b }, [x0] 34 ld2r { v15.4h, v16.4h }, [x15] 35 ld2r { v31.2s, v0.2s }, [sp] 36 ld2r { v31.1d, v0.1d }, [sp] 190 ld2r { v0.16b, v1.16b }, [x0], #2 191 ld2r { v15.8h, v16.8h }, [x15], #4 [all …]
|
D | arm64-simd-ldst.s | 904 ld2r: label 905 ld2r.8b {v4, v5}, [x2] 906 ld2r.8b {v4, v5}, [x2], x3 907 ld2r.16b {v4, v5}, [x2] 908 ld2r.16b {v4, v5}, [x2], x3 909 ld2r.4h {v4, v5}, [x2] 910 ld2r.4h {v4, v5}, [x2], x3 911 ld2r.8h {v4, v5}, [x2] 912 ld2r.8h {v4, v5}, [x2], x3 913 ld2r.2s {v4, v5}, [x2] [all …]
|
/external/llvm/test/MC/AArch64/ |
D | neon-simd-ldst-one-elem.s | 29 ld2r { v0.16b, v1.16b }, [x0] 30 ld2r { v15.8h, v16.8h }, [x15] 31 ld2r { v31.4s, v0.4s }, [sp] 32 ld2r { v0.2d, v1.2d }, [x0] 33 ld2r { v0.8b, v1.8b }, [x0] 34 ld2r { v15.4h, v16.4h }, [x15] 35 ld2r { v31.2s, v0.2s }, [sp] 36 ld2r { v31.1d, v0.1d }, [sp] 190 ld2r { v0.16b, v1.16b }, [x0], #2 191 ld2r { v15.8h, v16.8h }, [x15], #4 [all …]
|
D | arm64-simd-ldst.s | 904 ld2r: label 905 ld2r.8b {v4, v5}, [x2] 906 ld2r.8b {v4, v5}, [x2], x3 907 ld2r.16b {v4, v5}, [x2] 908 ld2r.16b {v4, v5}, [x2], x3 909 ld2r.4h {v4, v5}, [x2] 910 ld2r.4h {v4, v5}, [x2], x3 911 ld2r.8h {v4, v5}, [x2] 912 ld2r.8h {v4, v5}, [x2], x3 913 ld2r.2s {v4, v5}, [x2] [all …]
|
/external/llvm/test/CodeGen/AArch64/ |
D | arm64-ld1.ll | 557 ; CHECK: ld2r.8b { v0, v1 }, [x0] 559 %tmp2 = call %struct.__neon_int8x8x2_t @llvm.aarch64.neon.ld2r.v8i8.p0i8(i8* %A) 581 declare %struct.__neon_int8x8x2_t @llvm.aarch64.neon.ld2r.v8i8.p0i8(i8*) nounwind readonly 588 ; CHECK: ld2r.16b { v0, v1 }, [x0] 590 %tmp2 = call %struct.__neon_int8x16x2_t @llvm.aarch64.neon.ld2r.v16i8.p0i8(i8* %A) 612 declare %struct.__neon_int8x16x2_t @llvm.aarch64.neon.ld2r.v16i8.p0i8(i8*) nounwind readonly 619 ; CHECK: ld2r.4h { v0, v1 }, [x0] 621 %tmp2 = call %struct.__neon_int16x4x2_t @llvm.aarch64.neon.ld2r.v4i16.p0i16(i16* %A) 643 declare %struct.__neon_int16x4x2_t @llvm.aarch64.neon.ld2r.v4i16.p0i16(i16*) nounwind readonly 650 ; CHECK: ld2r.8h { v0, v1 }, [x0] [all …]
|
D | fp16-vector-load-store.ll | 224 declare { <4 x half>, <4 x half> } @llvm.aarch64.neon.ld2r.v4f16.p0f16(half*) 227 declare { <8 x half>, <8 x half> } @llvm.aarch64.neon.ld2r.v8f16.p0f16(half*) 234 ; CHECK: ld2r { v0.4h, v1.4h }, [x0] 236 %0 = tail call { <4 x half>, <4 x half> } @llvm.aarch64.neon.ld2r.v4f16.p0f16(half* %a) 261 ; CHECK: ld2r { v0.8h, v1.8h }, [x0] 263 %0 = tail call { <8 x half>, <8 x half> } @llvm.aarch64.neon.ld2r.v8f16.p0f16(half* %a)
|
D | arm64-indexed-vector-ldst.ll | 2128 ;CHECK: ld2r.16b { v0, v1 }, [x0], #2 2129 %ld2 = call { <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld2r.v16i8.p0i8(i8* %A) 2137 ;CHECK: ld2r.16b { v0, v1 }, [x0], x{{[0-9]+}} 2138 %ld2 = call { <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld2r.v16i8.p0i8(i8* %A) 2144 declare { <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld2r.v16i8.p0i8(i8*) nounwind readonly 2149 ;CHECK: ld2r.8b { v0, v1 }, [x0], #2 2150 %ld2 = call { <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld2r.v8i8.p0i8(i8* %A) 2158 ;CHECK: ld2r.8b { v0, v1 }, [x0], x{{[0-9]+}} 2159 %ld2 = call { <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld2r.v8i8.p0i8(i8* %A) 2165 declare { <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld2r.v8i8.p0i8(i8*) nounwind readonly [all …]
|
/external/llvm-project/llvm/test/CodeGen/AArch64/ |
D | arm64-ld1.ll | 557 ; CHECK: ld2r.8b { v0, v1 }, [x0] 559 %tmp2 = call %struct.__neon_int8x8x2_t @llvm.aarch64.neon.ld2r.v8i8.p0i8(i8* %A) 581 declare %struct.__neon_int8x8x2_t @llvm.aarch64.neon.ld2r.v8i8.p0i8(i8*) nounwind readonly 588 ; CHECK: ld2r.16b { v0, v1 }, [x0] 590 %tmp2 = call %struct.__neon_int8x16x2_t @llvm.aarch64.neon.ld2r.v16i8.p0i8(i8* %A) 612 declare %struct.__neon_int8x16x2_t @llvm.aarch64.neon.ld2r.v16i8.p0i8(i8*) nounwind readonly 619 ; CHECK: ld2r.4h { v0, v1 }, [x0] 621 %tmp2 = call %struct.__neon_int16x4x2_t @llvm.aarch64.neon.ld2r.v4i16.p0i16(i16* %A) 643 declare %struct.__neon_int16x4x2_t @llvm.aarch64.neon.ld2r.v4i16.p0i16(i16*) nounwind readonly 650 ; CHECK: ld2r.8h { v0, v1 }, [x0] [all …]
|
D | arm64_32-neon.ll | 33 declare {%vec, %vec} @llvm.aarch64.neon.ld2r.v2f64.p0i8(i8*) 36 ; CHECK: ld2r.2d { v0, v1 }, [x0] 37 %res = call {%vec, %vec} @llvm.aarch64.neon.ld2r.v2f64.p0i8(i8* %addr)
|
D | fp16-vector-load-store.ll | 302 declare { <4 x half>, <4 x half> } @llvm.aarch64.neon.ld2r.v4f16.p0f16(half*) 305 declare { <8 x half>, <8 x half> } @llvm.aarch64.neon.ld2r.v8f16.p0f16(half*) 312 ; CHECK: ld2r { v0.4h, v1.4h }, [x0] 314 %0 = tail call { <4 x half>, <4 x half> } @llvm.aarch64.neon.ld2r.v4f16.p0f16(half* %a) 339 ; CHECK: ld2r { v0.8h, v1.8h }, [x0] 341 %0 = tail call { <8 x half>, <8 x half> } @llvm.aarch64.neon.ld2r.v8f16.p0f16(half* %a)
|
D | arm64-indexed-vector-ldst.ll | 2128 ;CHECK: ld2r.16b { v0, v1 }, [x0], #2 2129 %ld2 = call { <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld2r.v16i8.p0i8(i8* %A) 2137 ;CHECK: ld2r.16b { v0, v1 }, [x0], x{{[0-9]+}} 2138 %ld2 = call { <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld2r.v16i8.p0i8(i8* %A) 2144 declare { <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld2r.v16i8.p0i8(i8*) nounwind readonly 2149 ;CHECK: ld2r.8b { v0, v1 }, [x0], #2 2150 %ld2 = call { <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld2r.v8i8.p0i8(i8* %A) 2158 ;CHECK: ld2r.8b { v0, v1 }, [x0], x{{[0-9]+}} 2159 %ld2 = call { <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld2r.v8i8.p0i8(i8* %A) 2165 declare { <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld2r.v8i8.p0i8(i8*) nounwind readonly [all …]
|
D | aarch64-bf16-ldst-intrinsics.ll | 451 ; CHECK-NEXT: ld2r { v0.4h, v1.4h }, [x0] 454 …%vld2 = tail call { <4 x bfloat>, <4 x bfloat> } @llvm.aarch64.neon.ld2r.v4bf16.p0bf16(bfloat* %pt… 463 declare { <4 x bfloat>, <4 x bfloat> } @llvm.aarch64.neon.ld2r.v4bf16.p0bf16(bfloat*) nounwind 468 ; CHECK-NEXT: ld2r { v0.8h, v1.8h }, [x0] 471 …%vld2 = tail call { <8 x bfloat>, <8 x bfloat> } @llvm.aarch64.neon.ld2r.v8bf16.p0bf16(bfloat* %pt… 480 declare { <8 x bfloat>, <8 x bfloat> } @llvm.aarch64.neon.ld2r.v8bf16.p0bf16(bfloat*) nounwind
|
/external/llvm-project/llvm/test/MC/Disassembler/AArch64/ |
D | arm64-advsimd.txt | 1074 # CHECK: ld2r.8b { v1, v2 }, [x1] 1075 # CHECK: ld2r.8b { v1, v2 }, [x1], x2 1076 # CHECK: ld2r.16b { v1, v2 }, [x1] 1077 # CHECK: ld2r.16b { v1, v2 }, [x1], x2 1078 # CHECK: ld2r.4h { v1, v2 }, [x1] 1079 # CHECK: ld2r.4h { v1, v2 }, [x1], x2 1080 # CHECK: ld2r.8h { v1, v2 }, [x1] 1081 # CHECK: ld2r.8h { v1, v2 }, [x1], x2 1082 # CHECK: ld2r.2s { v1, v2 }, [x1] 1083 # CHECK: ld2r.2s { v1, v2 }, [x1], x2 [all …]
|
/external/llvm/test/MC/Disassembler/AArch64/ |
D | arm64-advsimd.txt | 1074 # CHECK: ld2r.8b { v1, v2 }, [x1] 1075 # CHECK: ld2r.8b { v1, v2 }, [x1], x2 1076 # CHECK: ld2r.16b { v1, v2 }, [x1] 1077 # CHECK: ld2r.16b { v1, v2 }, [x1], x2 1078 # CHECK: ld2r.4h { v1, v2 }, [x1] 1079 # CHECK: ld2r.4h { v1, v2 }, [x1], x2 1080 # CHECK: ld2r.8h { v1, v2 }, [x1] 1081 # CHECK: ld2r.8h { v1, v2 }, [x1], x2 1082 # CHECK: ld2r.2s { v1, v2 }, [x1] 1083 # CHECK: ld2r.2s { v1, v2 }, [x1], x2 [all …]
|
/external/vixl/test/aarch64/ |
D | test-trace-aarch64.cc | 998 __ ld2r(v26.V16B(), v27.V16B(), MemOperand(x0)); in GenerateTestSequenceNEON() local 999 __ ld2r(v21.V16B(), v22.V16B(), MemOperand(x1, x2, PostIndex)); in GenerateTestSequenceNEON() local 1000 __ ld2r(v5.V16B(), v6.V16B(), MemOperand(x1, 2, PostIndex)); in GenerateTestSequenceNEON() local 1001 __ ld2r(v26.V1D(), v27.V1D(), MemOperand(x0)); in GenerateTestSequenceNEON() local 1002 __ ld2r(v14.V1D(), v15.V1D(), MemOperand(x1, x2, PostIndex)); in GenerateTestSequenceNEON() local 1003 __ ld2r(v23.V1D(), v24.V1D(), MemOperand(x1, 16, PostIndex)); in GenerateTestSequenceNEON() local 1004 __ ld2r(v11.V2D(), v12.V2D(), MemOperand(x0)); in GenerateTestSequenceNEON() local 1005 __ ld2r(v29.V2D(), v30.V2D(), MemOperand(x1, x2, PostIndex)); in GenerateTestSequenceNEON() local 1006 __ ld2r(v15.V2D(), v16.V2D(), MemOperand(x1, 16, PostIndex)); in GenerateTestSequenceNEON() local 1007 __ ld2r(v26.V2S(), v27.V2S(), MemOperand(x0)); in GenerateTestSequenceNEON() local [all …]
|
D | test-cpu-features-aarch64.cc | 1124 TEST_NEON(ld2r_0, ld2r(v0.V8B(), v1.V8B(), MemOperand(x2))) 1125 TEST_NEON(ld2r_1, ld2r(v0.V16B(), v1.V16B(), MemOperand(x2))) 1126 TEST_NEON(ld2r_2, ld2r(v0.V4H(), v1.V4H(), MemOperand(x2))) 1127 TEST_NEON(ld2r_3, ld2r(v0.V8H(), v1.V8H(), MemOperand(x2))) 1128 TEST_NEON(ld2r_4, ld2r(v0.V2S(), v1.V2S(), MemOperand(x2))) 1129 TEST_NEON(ld2r_5, ld2r(v0.V4S(), v1.V4S(), MemOperand(x2))) 1130 TEST_NEON(ld2r_6, ld2r(v0.V1D(), v1.V1D(), MemOperand(x2))) 1131 TEST_NEON(ld2r_7, ld2r(v0.V2D(), v1.V2D(), MemOperand(x2))) 1132 TEST_NEON(ld2r_8, ld2r(v0.V8B(), v1.V8B(), MemOperand(x2, 2, PostIndex))) 1133 TEST_NEON(ld2r_9, ld2r(v0.V16B(), v1.V16B(), MemOperand(x2, 2, PostIndex))) [all …]
|
/external/vixl/test/test-trace-reference/ |
D | log-disasm-colour | 862 0x~~~~~~~~~~~~~~~~ 4d60c01a ld2r {v26.16b, v27.16b}, [x0] 863 0x~~~~~~~~~~~~~~~~ 4de2c035 ld2r {v21.16b, v22.16b}, [x1], x2 864 0x~~~~~~~~~~~~~~~~ 4dffc025 ld2r {v5.16b, v6.16b}, [x1], #2 865 0x~~~~~~~~~~~~~~~~ 0d60cc1a ld2r {v26.1d, v27.1d}, [x0] 866 0x~~~~~~~~~~~~~~~~ 0de2cc2e ld2r {v14.1d, v15.1d}, [x1], x2 867 0x~~~~~~~~~~~~~~~~ 0dffcc37 ld2r {v23.1d, v24.1d}, [x1], #16 868 0x~~~~~~~~~~~~~~~~ 4d60cc0b ld2r {v11.2d, v12.2d}, [x0] 869 0x~~~~~~~~~~~~~~~~ 4de2cc3d ld2r {v29.2d, v30.2d}, [x1], x2 870 0x~~~~~~~~~~~~~~~~ 4dffcc2f ld2r {v15.2d, v16.2d}, [x1], #16 871 0x~~~~~~~~~~~~~~~~ 0d60c81a ld2r {v26.2s, v27.2s}, [x0] [all …]
|
D | log-disasm | 862 0x~~~~~~~~~~~~~~~~ 4d60c01a ld2r {v26.16b, v27.16b}, [x0] 863 0x~~~~~~~~~~~~~~~~ 4de2c035 ld2r {v21.16b, v22.16b}, [x1], x2 864 0x~~~~~~~~~~~~~~~~ 4dffc025 ld2r {v5.16b, v6.16b}, [x1], #2 865 0x~~~~~~~~~~~~~~~~ 0d60cc1a ld2r {v26.1d, v27.1d}, [x0] 866 0x~~~~~~~~~~~~~~~~ 0de2cc2e ld2r {v14.1d, v15.1d}, [x1], x2 867 0x~~~~~~~~~~~~~~~~ 0dffcc37 ld2r {v23.1d, v24.1d}, [x1], #16 868 0x~~~~~~~~~~~~~~~~ 4d60cc0b ld2r {v11.2d, v12.2d}, [x0] 869 0x~~~~~~~~~~~~~~~~ 4de2cc3d ld2r {v29.2d, v30.2d}, [x1], x2 870 0x~~~~~~~~~~~~~~~~ 4dffcc2f ld2r {v15.2d, v16.2d}, [x1], #16 871 0x~~~~~~~~~~~~~~~~ 0d60c81a ld2r {v26.2s, v27.2s}, [x0] [all …]
|
D | log-cpufeatures-custom | 861 0x~~~~~~~~~~~~~~~~ 4d60c01a ld2r {v26.16b, v27.16b}, [x0] ### {NEON} ### 862 0x~~~~~~~~~~~~~~~~ 4de2c035 ld2r {v21.16b, v22.16b}, [x1], x2 ### {NEON} ### 863 0x~~~~~~~~~~~~~~~~ 4dffc025 ld2r {v5.16b, v6.16b}, [x1], #2 ### {NEON} ### 864 0x~~~~~~~~~~~~~~~~ 0d60cc1a ld2r {v26.1d, v27.1d}, [x0] ### {NEON} ### 865 0x~~~~~~~~~~~~~~~~ 0de2cc2e ld2r {v14.1d, v15.1d}, [x1], x2 ### {NEON} ### 866 0x~~~~~~~~~~~~~~~~ 0dffcc37 ld2r {v23.1d, v24.1d}, [x1], #16 ### {NEON} ### 867 0x~~~~~~~~~~~~~~~~ 4d60cc0b ld2r {v11.2d, v12.2d}, [x0] ### {NEON} ### 868 0x~~~~~~~~~~~~~~~~ 4de2cc3d ld2r {v29.2d, v30.2d}, [x1], x2 ### {NEON} ### 869 0x~~~~~~~~~~~~~~~~ 4dffcc2f ld2r {v15.2d, v16.2d}, [x1], #16 ### {NEON} ### 870 0x~~~~~~~~~~~~~~~~ 0d60c81a ld2r {v26.2s, v27.2s}, [x0] ### {NEON} ### [all …]
|
D | log-cpufeatures-colour | 861 0x~~~~~~~~~~~~~~~~ 4d60c01a ld2r {v26.16b, v27.16b}, [x0] [1;35mNEON[0;m 862 0x~~~~~~~~~~~~~~~~ 4de2c035 ld2r {v21.16b, v22.16b}, [x1], x2 [1;35mNEON[0;m 863 0x~~~~~~~~~~~~~~~~ 4dffc025 ld2r {v5.16b, v6.16b}, [x1], #2 [1;35mNEON[0;m 864 0x~~~~~~~~~~~~~~~~ 0d60cc1a ld2r {v26.1d, v27.1d}, [x0] [1;35mNEON[0;m 865 0x~~~~~~~~~~~~~~~~ 0de2cc2e ld2r {v14.1d, v15.1d}, [x1], x2 [1;35mNEON[0;m 866 0x~~~~~~~~~~~~~~~~ 0dffcc37 ld2r {v23.1d, v24.1d}, [x1], #16 [1;35mNEON[0;m 867 0x~~~~~~~~~~~~~~~~ 4d60cc0b ld2r {v11.2d, v12.2d}, [x0] [1;35mNEON[0;m 868 0x~~~~~~~~~~~~~~~~ 4de2cc3d ld2r {v29.2d, v30.2d}, [x1], x2 [1;35mNEON[0;m 869 0x~~~~~~~~~~~~~~~~ 4dffcc2f ld2r {v15.2d, v16.2d}, [x1], #16 [1;35mNEON[0;m 870 0x~~~~~~~~~~~~~~~~ 0d60c81a ld2r {v26.2s, v27.2s}, [x0] [1;35mNEON[0;m [all …]
|
D | log-cpufeatures | 861 0x~~~~~~~~~~~~~~~~ 4d60c01a ld2r {v26.16b, v27.16b}, [x0] // Needs: NEON 862 0x~~~~~~~~~~~~~~~~ 4de2c035 ld2r {v21.16b, v22.16b}, [x1], x2 // Needs: NEON 863 0x~~~~~~~~~~~~~~~~ 4dffc025 ld2r {v5.16b, v6.16b}, [x1], #2 // Needs: NEON 864 0x~~~~~~~~~~~~~~~~ 0d60cc1a ld2r {v26.1d, v27.1d}, [x0] // Needs: NEON 865 0x~~~~~~~~~~~~~~~~ 0de2cc2e ld2r {v14.1d, v15.1d}, [x1], x2 // Needs: NEON 866 0x~~~~~~~~~~~~~~~~ 0dffcc37 ld2r {v23.1d, v24.1d}, [x1], #16 // Needs: NEON 867 0x~~~~~~~~~~~~~~~~ 4d60cc0b ld2r {v11.2d, v12.2d}, [x0] // Needs: NEON 868 0x~~~~~~~~~~~~~~~~ 4de2cc3d ld2r {v29.2d, v30.2d}, [x1], x2 // Needs: NEON 869 0x~~~~~~~~~~~~~~~~ 4dffcc2f ld2r {v15.2d, v16.2d}, [x1], #16 // Needs: NEON 870 0x~~~~~~~~~~~~~~~~ 0d60c81a ld2r {v26.2s, v27.2s}, [x0] // Needs: NEON [all …]
|
D | log-all | 3943 0x~~~~~~~~~~~~~~~~ 4d60c01a ld2r {v26.16b, v27.16b}, [x0] 3947 0x~~~~~~~~~~~~~~~~ 4de2c035 ld2r {v21.16b, v22.16b}, [x1], x2 3952 0x~~~~~~~~~~~~~~~~ 4dffc025 ld2r {v5.16b, v6.16b}, [x1], #2 3957 0x~~~~~~~~~~~~~~~~ 0d60cc1a ld2r {v26.1d, v27.1d}, [x0] 3961 0x~~~~~~~~~~~~~~~~ 0de2cc2e ld2r {v14.1d, v15.1d}, [x1], x2 3966 0x~~~~~~~~~~~~~~~~ 0dffcc37 ld2r {v23.1d, v24.1d}, [x1], #16 3971 0x~~~~~~~~~~~~~~~~ 4d60cc0b ld2r {v11.2d, v12.2d}, [x0] 3975 0x~~~~~~~~~~~~~~~~ 4de2cc3d ld2r {v29.2d, v30.2d}, [x1], x2 3980 0x~~~~~~~~~~~~~~~~ 4dffcc2f ld2r {v15.2d, v16.2d}, [x1], #16 3985 0x~~~~~~~~~~~~~~~~ 0d60c81a ld2r {v26.2s, v27.2s}, [x0] [all …]
|
/external/capstone/arch/AArch64/ |
D | AArch64MappingInsnOp.inc | 3113 { /* AArch64_LD2Rv16b, ARM64_INS_LD2R: ld2r $vt, [$rn] */ 3117 { /* AArch64_LD2Rv16b_POST, ARM64_INS_LD2R: ld2r $vt, [$rn], $xm */ 3121 { /* AArch64_LD2Rv1d, ARM64_INS_LD2R: ld2r $vt, [$rn] */ 3125 { /* AArch64_LD2Rv1d_POST, ARM64_INS_LD2R: ld2r $vt, [$rn], $xm */ 3129 { /* AArch64_LD2Rv2d, ARM64_INS_LD2R: ld2r $vt, [$rn] */ 3133 { /* AArch64_LD2Rv2d_POST, ARM64_INS_LD2R: ld2r $vt, [$rn], $xm */ 3137 { /* AArch64_LD2Rv2s, ARM64_INS_LD2R: ld2r $vt, [$rn] */ 3141 { /* AArch64_LD2Rv2s_POST, ARM64_INS_LD2R: ld2r $vt, [$rn], $xm */ 3145 { /* AArch64_LD2Rv4h, ARM64_INS_LD2R: ld2r $vt, [$rn] */ 3149 { /* AArch64_LD2Rv4h_POST, ARM64_INS_LD2R: ld2r $vt, [$rn], $xm */ [all …]
|