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Searched refs:ldc2 (Results 1 – 25 of 131) sorted by relevance

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/external/llvm-project/llvm/test/MC/Disassembler/ARM/
Dbfloat16-a32_1.txt26 # NOBF16-NEXT: ldc2 p8, c0, [r0], #-320
30 # NOBF16-NEXT: ldc2 p8, c0, [r0], #-504
34 # NOBF16-NEXT: ldc2 p8, c0, [lr], #-832
38 # NOBF16-NEXT: ldc2 p8, c0, [lr], #-1016
42 # NOBF16-NEXT: ldc2 p8, c0, [r0], #-832
46 # NOBF16-NEXT: ldc2 p8, c14, [r0], #-320
54 # NOBF16-NEXT: ldc2 p8, c0, [r0], #-64
58 # NOBF16-NEXT: ldc2 p8, c0, [r0], #-248
62 # NOBF16-NEXT: ldc2 p8, c0, [lr], #-576
66 # NOBF16-NEXT: ldc2 p8, c0, [lr], #-760
[all …]
Dinvalid-armv8.txt154 # CHECK-V7: ldc2
159 # CHECK-V7: ldc2
164 # CHECK-V7: ldc2
Dinvalid-thumbv8.txt154 # CHECK-V7: ldc2
159 # CHECK-V7: ldc2
164 # CHECK-V7: ldc2
/external/llvm/test/MC/Mips/mips32r6/
Dinvalid-mips5-wrong-error.s12ldc2 $1, -2049($12) # CHECK: :[[@LINE]]:9: error: instruction requires a CPU feature not…
13ldc2 $1, 2048($12) # CHECK: :[[@LINE]]:9: error: instruction requires a CPU feature not…
14ldc2 $1, 1023($32) # CHECK: :[[@LINE]]:18: error: expected memory with 16-bit signed of…
/external/llvm-project/llvm/test/MC/ARM/
Dcde-integer.s14 ldc2 p1, c8, [r1, #4] label
16 ldc2 p0, c7, [r2] label
18 ldc2 p1, c6, [r3, #-224] label
20 ldc2 p0, c5, [r4, #-120]! label
/external/llvm-project/llvm/test/MC/Mips/mips1/
Dinvalid-mips2-wrong-error.s9ldc2 $8,-21181($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
10ldc2 $8,-1024($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
Dinvalid-mips3-wrong-error.s9ldc2 $8,-21181($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
10ldc2 $20,-1024($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
Dinvalid-mips4-wrong-error.s11ldc2 $8,-21181($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
12ldc2 $20,-1024($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
/external/llvm/test/MC/Mips/mips1/
Dinvalid-mips2-wrong-error.s9ldc2 $8,-21181($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signe…
10ldc2 $8,-1024($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signe…
Dinvalid-mips3-wrong-error.s9ldc2 $8,-21181($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit sig…
10ldc2 $20,-1024($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit sig…
Dinvalid-mips4-wrong-error.s11ldc2 $8,-21181($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit sig…
12ldc2 $20,-1024($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit sig…
/external/llvm-project/llvm/test/MC/Mips/mips32r6/
Dinvalid-mips5-wrong-error.s12ldc2 $1, -2049($12) # CHECK: :[[@LINE]]:9: error: instruction requires a CPU feature not…
13ldc2 $1, 2048($12) # CHECK: :[[@LINE]]:9: error: instruction requires a CPU feature not…
/external/llvm/test/MC/Mips/micromips32r6/
Dinvalid-wrong-error.s31ldc2 $1, -2049($12) # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not curr…
32ldc2 $1, 2048($12) # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not curr…
33 ldc2 $1, 1023($32) # CHECK: :[[@LINE]]:12: error: expected memory with 16-bit signed offset
/external/llvm/test/MC/Mips/micromips64r6/
Dinvalid-wrong-error.s41ldc2 $1, -2049($12) # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not curr…
42ldc2 $1, 2048($12) # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not curr…
43 ldc2 $1, 1023($32) # CHECK: :[[@LINE]]:12: error: expected memory with 16-bit signed offset
/external/llvm-project/llvm/test/CodeGen/ARM/
Dintrinsics-coprocessor.ll25 ; CHECK: ldc2 p7, c3, [r{{[0-9]+}}]
26 tail call void @llvm.arm.ldc2(i32 7, i32 3, i8* %i) nounwind
48 declare void @llvm.arm.ldc2(i32, i32, i8*) nounwind
/external/llvm/test/CodeGen/ARM/
Dintrinsics-coprocessor.ll26 ; CHECK: ldc2 p7, c3, [r{{[0-9]+}}]
27 tail call void @llvm.arm.ldc2(i32 7, i32 3, i8* %i) nounwind
49 declare void @llvm.arm.ldc2(i32, i32, i8*) nounwind
/external/llvm-project/llvm/test/CodeGen/Thumb2/
Dintrinsics-coprocessor.ll24 ; CHECK: ldc2 p7, c3, [r{{[0-9]+}}]
25 tail call void @llvm.arm.ldc2(i32 7, i32 3, i8* %i) nounwind
63 declare void @llvm.arm.ldc2(i32, i32, i8*) nounwind
/external/llvm/test/MC/Disassembler/ARM/
Dinvalid-thumbv8.txt154 # CHECK-V7: ldc2
159 # CHECK-V7: ldc2
164 # CHECK-V7: ldc2
Dinvalid-armv8.txt154 # CHECK-V7: ldc2
159 # CHECK-V7: ldc2
164 # CHECK-V7: ldc2
/external/llvm-project/llvm/test/MC/Mips/micromips32r6/
Dinvalid-wrong-error.s17ldc2 $1, -2049($12) # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not curr…
18ldc2 $1, 2048($12) # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not curr…
/external/clang/test/CodeGen/
Dbuiltins-arm.c103 void ldc2(const void *i) { in ldc2() function
/external/llvm-project/libunwind/src/
DUnwindRegistersRestore.S751 ldc2 p1, cr8, [r0], #4 @ wldrw wCGR0, [r0], #4
752 ldc2 p1, cr9, [r0], #4 @ wldrw wCGR1, [r0], #4
753 ldc2 p1, cr10, [r0], #4 @ wldrw wCGR2, [r0], #4
754 ldc2 p1, cr11, [r0], #4 @ wldrw wCGR3, [r0], #4
/external/llvm-project/clang/test/CodeGen/
Dbuiltins-arm.c118 void ldc2(const void *i) { in ldc2() function
/external/capstone/suite/MC/ARM/
Dbasic-thumb2-instructions.s.cs219 0x91,0xfd,0x01,0x80 = ldc2 p0, c8, [r1, #4]
220 0x92,0xfd,0x00,0x71 = ldc2 p1, c7, [r2]
221 0x13,0xfd,0x38,0x62 = ldc2 p2, c6, [r3, #-224]
222 0x34,0xfd,0x1e,0x53 = ldc2 p3, c5, [r4, #-120]!
223 0xb5,0xfc,0x04,0x44 = ldc2 p4, c4, [r5], #16
224 0x36,0xfc,0x12,0x35 = ldc2 p5, c3, [r6], #-72
243 0x91,0xfc,0x19,0x82 = ldc2 p2, c8, [r1], {25}
/external/llvm/test/MC/Mips/mips2/
Dvalid.s69ldc2 $8,-21181($at) # CHECK: ldc2 $8, -21181($1) # encoding: [0xd8,0x28,0xad,0x43]

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