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Searched refs:ldd (Results 1 – 25 of 161) sorted by relevance

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/external/mesa3d/src/mesa/sparc/
Dsparc_matrix.h41 ldd [BASE + ( 0 * 0x4)], M0; \
42 ldd [BASE + ( 2 * 0x4)], M2; \
43 ldd [BASE + (12 * 0x4)], M12; \
44 ldd [BASE + (14 * 0x4)], M14
47 ldd [BASE + ( 0 * 0x4)], M0; \
48 ldd [BASE + (12 * 0x4)], M12
52 ldd [BASE + (12 * 0x4)], M12
55 ldd [BASE + ( 0 * 0x4)], M0; \
57 ldd [BASE + (12 * 0x4)], M12; \
62 ldd [BASE + (12 * 0x4)], M12; \
[all …]
/external/llvm-project/llvm/test/MC/AVR/
Dinst-ldd.s5 ldd r2, Y+2
6 ldd r0, Y+0
8 ldd r9, Z+12
9 ldd r7, Z+30
11 ldd r9, Z+foo
13 ; CHECK: ldd r2, Y+2 ; encoding: [0x2a,0x80]
14 ; CHECK: ldd r0, Y+0 ; encoding: [0x08,0x80]
16 ; CHECK: ldd r9, Z+12 ; encoding: [0x94,0x84]
17 ; CHECK: ldd r7, Z+30 ; encoding: [0x76,0x8c]
19 ; CHECK: ldd r9, Z+foo ; encoding: [0x90'A',0x80'A']
/external/python/cpython2/Modules/_ctypes/libffi/src/sparc/
Dv9.S60 ldd [%l0+ARGS], %f0
61 ldd [%l0+ARGS+8], %f2
62 ldd [%l0+ARGS+16], %f4
63 ldd [%l0+ARGS+24], %f6
64 ldd [%l0+ARGS+32], %f8
65 ldd [%l0+ARGS+40], %f10
66 ldd [%l0+ARGS+48], %f12
67 ldd [%l0+ARGS+56], %f14
68 ldd [%l0+ARGS+64], %f16
69 ldd [%l0+ARGS+72], %f18
[all …]
/external/llvm/test/MC/Sparc/
Dsparc-coproc.s15 ! CHECK: ldd [%i1], %c4 ! encoding: [0xc9,0x9e,0x40,0x00]
16 ! CHECK: ldd [%i7], %c4 ! encoding: [0xc9,0x9f,0xc0,0x00]
17 ! CHECK: ldd [%i7+200], %c4 ! encoding: [0xc9,0x9f,0xe0,0xc8]
18 ! CHECK: ldd [%i7+%o3], %c4 ! encoding: [0xc9,0x9f,0xc0,0x0b]
19 ! CHECK: ldd [%i1], %c30 ! encoding: [0xfd,0x9e,0x40,0x00]
20 ldd [%i1], %c4
21 ldd [%i7], %c4
22 ldd [%i7 + 200], %c4
23 ldd [%i7+%o3], %c4
24 ldd [%i1], %c30
Dsparc-mem-instructions.s49 ! CHECK: ldd [%i0+%l6], %o2 ! encoding: [0xd4,0x1e,0x00,0x16]
50 ldd [%i0 + %l6], %o2
51 ! CHECK: ldd [%i0+32], %o2 ! encoding: [0xd4,0x1e,0x20,0x20]
52 ldd [%i0 + 32], %o2
53 ! CHECK: ldd [%g1], %o2 ! encoding: [0xd4,0x18,0x40,0x00]
54 ldd [%g1], %o2
/external/llvm-project/llvm/test/MC/Sparc/
Dsparc-coproc.s15 ! CHECK: ldd [%i1], %c4 ! encoding: [0xc9,0x9e,0x40,0x00]
16 ! CHECK: ldd [%i7], %c4 ! encoding: [0xc9,0x9f,0xc0,0x00]
17 ! CHECK: ldd [%i7+200], %c4 ! encoding: [0xc9,0x9f,0xe0,0xc8]
18 ! CHECK: ldd [%i7+%o3], %c4 ! encoding: [0xc9,0x9f,0xc0,0x0b]
19 ! CHECK: ldd [%i1], %c30 ! encoding: [0xfd,0x9e,0x40,0x00]
20 ldd [%i1], %c4
21 ldd [%i7], %c4
22 ldd [%i7 + 200], %c4
23 ldd [%i7+%o3], %c4
24 ldd [%i1], %c30
Dsparc-mem-instructions.s49 ! CHECK: ldd [%i0+%l6], %o2 ! encoding: [0xd4,0x1e,0x00,0x16]
50 ldd [%i0 + %l6], %o2
51 ! CHECK: ldd [%i0+32], %o2 ! encoding: [0xd4,0x1e,0x20,0x20]
52 ldd [%i0 + 32], %o2
53 ! CHECK: ldd [%g1], %o2 ! encoding: [0xd4,0x18,0x40,0x00]
54 ldd [%g1], %o2
/external/llvm-project/llvm/test/CodeGen/AVR/
Dreturn.ll99 ; CHECK: ldd r18, Y+5
100 ; CHECK: ldd r19, Y+6
101 ; CHECK: ldd r20, Y+7
102 ; CHECK: ldd r21, Y+8
103 ; CHECK: ldd r22, Y+9
104 ; CHECK: ldd r23, Y+10
105 ; CHECK: ldd r24, Y+11
106 ; CHECK: ldd r25, Y+12
116 ; CHECK: ldd r22, Y+5
117 ; CHECK: ldd r23, Y+6
[all …]
Dvarargs.ll14 ; CHECK: ldd r22, Y+39
15 ; CHECK: ldd r23, Y+40
30 ; CHECK: ldd r24, [[REG:X|Y|Z]]+{{[0-9]+}}
31 ; CHECK: ldd r25, [[REG]]+{{[0-9]+}}
/external/libffi/src/sparc/
Dv9.S73 ldd [%sp+STACK_BIAS+128], %f0 ! load all fp arg regs
74 ldd [%sp+STACK_BIAS+128+8], %f2
75 ldd [%sp+STACK_BIAS+128+16], %f4
76 ldd [%sp+STACK_BIAS+128+24], %f6
77 ldd [%sp+STACK_BIAS+128+32], %f8
78 ldd [%sp+STACK_BIAS+128+40], %f10
79 ldd [%sp+STACK_BIAS+128+48], %f12
80 ldd [%sp+STACK_BIAS+128+56], %f14
81 ldd [%sp+STACK_BIAS+128+64], %f16
82 ldd [%sp+STACK_BIAS+128+72], %f18
[all …]
/external/e2fsprogs/debian/scripts/
Dtest-backtrace26 if ! ldd /tmp/backtrace$$ > /tmp/backtrace$$.ldd 2>&1 ; then
30 grep -q /usr/lib /tmp/backtrace$$.ldd
/external/llvm-project/llvm/test/CodeGen/AVR/calling-conv/c/
Dstack.ll14 ; CHECK-NEXT: ldd r24, Y+7
15 ; CHECK-NEXT: ldd r25, Y+8
21 ; CHECK-NEXT: ldd r24, Y+5
22 ; CHECK-NEXT: ldd r25, Y+6
/external/ltp/
Dver_linux94 ls -l `ldd /bin/sh | awk '/libc/{print $3}'` | sed \
98 ldd -v > /dev/null 2>&1 && ldd -v || ldd --version |head -n 1 | awk \
/external/llvm-project/llvm/test/CodeGen/SPARC/
Dfp128.ll7 ; CHECK: ldd
8 ; CHECK: ldd
9 ; CHECK: ldd
10 ; CHECK: ldd
43 ; CHECK-DAG: ldd [%[[S0]]], %f{{.+}}
44 ; CHECK-DAG: ldd [%[[S1]]], %f{{.+}}
65 ; CHECK-NEXT: ldd [%g1], %f{{.+}}
68 ; CHECK-NEXT: ldd [%g1+8], %f{{.+}}
113 ; CHECK: ldd [%o0], %f0
114 ; CHECK: ldd [%o0+8], %f2
[all …]
/external/llvm/test/CodeGen/SPARC/
Dfp128.ll8 ; CHECK: ldd
9 ; CHECK: ldd
10 ; CHECK: ldd
11 ; CHECK: ldd
40 ; CHECK-DAG: ldd [%[[S0]]], %f{{.+}}
41 ; CHECK-DAG: ldd [%[[S1]]], %f{{.+}}
86 ; CHECK: ldd [%o0], %f0
87 ; CHECK: ldd [%o0+8], %f2
207 ; CHECK: ldd [%o0], %f0
208 ; CHECK: ldd [%o0+8], %f2
/external/llvm/test/MC/Disassembler/Sparc/
Dsparc-mem.txt75 # CHECK: ldd [%i0+%l6], %f2
78 # CHECK: ldd [%i0+32], %f2
81 # CHECK: ldd [%g1], %f2
84 # CHECK: ldd [%g1], %f2
225 # CHECK: ldd [%i0+%l6], %o2
228 # CHECK: ldd [%i0+32], %o2
231 # CHECK: ldd [%g1], %o2
234 # CHECK: ldd [%g1], %o2
/external/llvm-project/llvm/test/MC/Disassembler/Sparc/
Dsparc-mem.txt75 # CHECK: ldd [%i0+%l6], %f2
78 # CHECK: ldd [%i0+32], %f2
81 # CHECK: ldd [%g1], %f2
84 # CHECK: ldd [%g1], %f2
225 # CHECK: ldd [%i0+%l6], %o2
228 # CHECK: ldd [%i0+32], %o2
231 # CHECK: ldd [%g1], %o2
234 # CHECK: ldd [%g1], %o2
/external/llvm-project/llvm/test/CodeGen/Hexagon/
Dcirc_ldd_bug.ll17 declare i8* @llvm.hexagon.circ.ldd(i8*, i8*, i32, i32) nounwind
32 %4 = call i8* @llvm.hexagon.circ.ldd(i8* %2, i8* %3, i32 %or, i32 -8)
74 %11 = call i8* @llvm.hexagon.circ.ldd(i8* %4, i8* %3, i32 %or, i32 -8)
88 %16 = call i8* @llvm.hexagon.circ.ldd(i8* %var8.0.in8.unr, i8* %3, i32 %or, i32 -8)
102 %21 = call i8* @llvm.hexagon.circ.ldd(i8* %var8.0.in8.unr19, i8* %3, i32 %or, i32 -8)
116 %26 = call i8* @llvm.hexagon.circ.ldd(i8* %var8.0.in8.unr28, i8* %3, i32 %or, i32 -8)
130 %31 = call i8* @llvm.hexagon.circ.ldd(i8* %var8.0.in8.unr37, i8* %3, i32 %or, i32 -8)
144 %36 = call i8* @llvm.hexagon.circ.ldd(i8* %var8.0.in8.unr46, i8* %3, i32 %or, i32 -8)
158 %41 = call i8* @llvm.hexagon.circ.ldd(i8* %var8.0.in8.unr55, i8* %3, i32 %or, i32 -8)
184 %47 = call i8* @llvm.hexagon.circ.ldd(i8* %var8.0.in8, i8* %3, i32 %or, i32 -8)
[all …]
/external/llvm/test/CodeGen/Hexagon/
Dcirc_ldd_bug.ll17 declare i8* @llvm.hexagon.circ.ldd(i8*, i8*, i32, i32) nounwind
32 %4 = call i8* @llvm.hexagon.circ.ldd(i8* %2, i8* %3, i32 %or, i32 -8)
74 %11 = call i8* @llvm.hexagon.circ.ldd(i8* %4, i8* %3, i32 %or, i32 -8)
88 %16 = call i8* @llvm.hexagon.circ.ldd(i8* %var8.0.in8.unr, i8* %3, i32 %or, i32 -8)
102 %21 = call i8* @llvm.hexagon.circ.ldd(i8* %var8.0.in8.unr19, i8* %3, i32 %or, i32 -8)
116 %26 = call i8* @llvm.hexagon.circ.ldd(i8* %var8.0.in8.unr28, i8* %3, i32 %or, i32 -8)
130 %31 = call i8* @llvm.hexagon.circ.ldd(i8* %var8.0.in8.unr37, i8* %3, i32 %or, i32 -8)
144 %36 = call i8* @llvm.hexagon.circ.ldd(i8* %var8.0.in8.unr46, i8* %3, i32 %or, i32 -8)
158 %41 = call i8* @llvm.hexagon.circ.ldd(i8* %var8.0.in8.unr55, i8* %3, i32 %or, i32 -8)
184 %47 = call i8* @llvm.hexagon.circ.ldd(i8* %var8.0.in8, i8* %3, i32 %or, i32 -8)
[all …]
/external/ltp/testcases/commands/
D.gitignore1 /ldd/datafiles/lddfile.out
2 /ldd/datafiles/*.obj.so
/external/llvm-project/llvm/test/CodeGen/AVR/atomics/
Dload16.ll7 ; CHECK-NEXT: ldd [[RR:r[0-9]+]], [[RD]]+1
33 ; CHECK-NEXT: ldd [[RR2:r[0-9]+]], [[RD]]+1
48 ; CHECK-NEXT: ldd [[RR2:r[0-9]+]], [[RD]]+1
63 ; CHECK-NEXT: ldd [[RR2:r[0-9]+]], [[RD]]+1
78 ; CHECK-NEXT: ldd [[RR2:r[0-9]+]], [[RD]]+1
93 ; CHECK-NEXT: ldd [[RR2:r[0-9]+]], [[RD]]+1
/external/llvm-project/llvm/test/Transforms/InstCombine/
Dpr25342.ll42 %ldd.sroa.0.0 = phi i32 [ 0, %entry ], [ %5, %for.body ]
43 %ldd.sroa.6.0 = phi i32 [ 0, %entry ], [ %7, %for.body ]
59 %4 = bitcast i32 %ldd.sroa.0.0 to float
62 %6 = bitcast i32 %ldd.sroa.6.0 to float
69 store i32 %ldd.sroa.0.0, i32* bitcast (%"struct.std::complex"* @dd to i32*), align 4
70 …store i32 %ldd.sroa.6.0, i32* bitcast (float* getelementptr inbounds (%"struct.std::complex", %"st…
112 %ldd.sroa.0.0 = phi i32 [ 0, %entry ], [ %9, %odd.bb ]
125 %4 = bitcast i32 %ldd.sroa.0.0 to float
144 store i32 %ldd.sroa.0.0, i32* bitcast (%"struct.std::complex"* @dd to i32*), align 4
/external/harfbuzz_ng/src/
Dcheck-libstdc++.sh11 if which ldd 2>/dev/null >/dev/null; then
12 LDD=ldd
/external/llvm-project/llvm/test/CodeGen/AVR/pseudo/
DLDDWRdYQ.mir21 ; CHECK: ldd r30, Y+1
22 ; CHECK-NEXT: ldd r31, Y+2
DLDDWRdPtrQ.mir21 ; CHECK: ldd r24, Z+10
22 ; CHECK-NEXT: ldd r25, Z+11

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