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Searched refs:ldff1w (Results 1 – 20 of 20) sorted by relevance

/external/llvm-project/llvm/test/MC/AArch64/SVE/
Dldff1w-diagnostics.s6 ldff1w z12.b, p7/z, [x0] label
11 ldff1w z4.h, p7/z, [x0] label
19 ldff1w z12.s, p8/z, [x0] label
24 ldff1w z4.d, p8/z, [x0] label
32 ldff1w z0.s, p0/z, [x0, sp] label
37 ldff1w z0.s, p0/z, [x0, x0, lsl #3] label
42 ldff1w z0.s, p0/z, [x0, w0] label
47 ldff1w z0.s, p0/z, [x0, w0, uxtw] label
56 ldff1w z0.d, p0/z, [x0, z0.h] label
61 ldff1w z0.d, p0/z, [x0, z0.s] label
[all …]
Dldff1w.s10 ldff1w { z31.d }, p7/z, [sp] label
16 ldff1w { z31.s }, p7/z, [sp] label
22 ldff1w { z31.d }, p7/z, [sp, xzr, lsl #2] label
28 ldff1w { z31.s }, p7/z, [sp, xzr, lsl #2] label
34 ldff1w { z0.s }, p0/z, [x0, x0, lsl #2] label
40 ldff1w { z0.d }, p0/z, [x0, x0, lsl #2] label
46 ldff1w { z0.s }, p0/z, [x0, z0.s, uxtw] label
52 ldff1w { z0.s }, p0/z, [x0, z0.s, sxtw] label
58 ldff1w { z31.s }, p7/z, [sp, z31.s, uxtw #2] label
64 ldff1w { z31.s }, p7/z, [sp, z31.s, sxtw #2] label
[all …]
/external/llvm-project/llvm/test/CodeGen/AArch64/
Dsve-intrinsics-loads-ff.ll285 define <vscale x 4 x i32> @ldff1w(<vscale x 4 x i1> %pg, i32* %a) {
286 ; CHECK-LABEL: ldff1w:
287 ; CHECK: ldff1w { z0.s }, p0/z, [x0]
295 ; CHECK: ldff1w { z0.s }, p0/z, [x0, x1, lsl #2]
304 ; CHECK: ldff1w { z0.d }, p0/z, [x0]
313 ; CHECK: ldff1w { z0.d }, p0/z, [x0, x1, lsl #2]
323 ; CHECK: ldff1w { z0.s }, p0/z, [x0]
331 ; CHECK: ldff1w { z0.s }, p0/z, [x0, x1, lsl #2]
340 ; CHECK: ldff1w { z0.d }, p0/z, [x0]
348 ; CHECK: ldff1w { z0.d }, p0/z, [x0, x1, lsl #2]
Dsve-intrinsics-ff-gather-loads-32bit-scaled-offsets.ll61 ; CHECK: ldff1w { z0.s }, p0/z, [x0, z0.s, uxtw #2]
71 ; CHECK: ldff1w { z0.s }, p0/z, [x0, z0.s, sxtw #2]
81 ; CHECK: ldff1w { z0.d }, p0/z, [x0, z0.d, uxtw #2]
92 ; CHECK: ldff1w { z0.d }, p0/z, [x0, z0.d, sxtw #2]
103 ; CHECK: ldff1w { z0.s }, p0/z, [x0, z0.s, uxtw #2]
113 ; CHECK: ldff1w { z0.s }, p0/z, [x0, z0.s, sxtw #2]
Dsve-intrinsics-ff-gather-loads-32bit-unscaled-offsets.ll106 ; CHECK: ldff1w { z0.s }, p0/z, [x0, z0.s, uxtw]
116 ; CHECK: ldff1w { z0.s }, p0/z, [x0, z0.s, sxtw]
126 ; CHECK: ldff1w { z0.d }, p0/z, [x0, z0.d, uxtw]
137 ; CHECK: ldff1w { z0.d }, p0/z, [x0, z0.d, sxtw]
148 ; CHECK: ldff1w { z0.s }, p0/z, [x0, z0.s, uxtw]
158 ; CHECK: ldff1w { z0.s }, p0/z, [x0, z0.s, sxtw]
Dsve-intrinsics-ff-gather-loads-vector-base-imm-offset.ll61 ; CHECK: ldff1w { z0.s }, p0/z, [z0.s, #16]
71 ; CHECK: ldff1w { z0.d }, p0/z, [z0.d, #16]
82 ; CHECK: ldff1w { z0.s }, p0/z, [z0.s, #16]
233 ; CHECK-NEXT: ldff1w { z0.s }, p0/z, [x8, z0.s, uxtw]
244 ; CHECK-NEXT: ldff1w { z0.d }, p0/z, [x8, z0.d]
256 ; CHECK-NEXT: ldff1w { z0.s }, p0/z, [x8, z0.s, uxtw]
Dsve-intrinsics-ff-gather-loads-vector-base-scalar-offset.ll61 ; CHECK: ldff1w { z0.s }, p0/z, [x0, z0.s, uxtw]
71 ; CHECK: ldff1w { z0.d }, p0/z, [x0, z0.d]
82 ; CHECK: ldff1w { z0.s }, p0/z, [x0, z0.s, uxtw]
Dsve-intrinsics-ff-gather-loads-64bit-scaled-offset.ll25 ; CHECK: ldff1w { z0.d }, p0/z, [x0, z0.d, lsl #2]
Dsve-intrinsics-ff-gather-loads-64bit-unscaled-offset.ll36 ; CHECK: ldff1w { z0.d }, p0/z, [x0, z0.d]
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/
DAArch64GenAsmMatcher.inc12526 "f1sw\006ldff1w\003ldg\004ldgm\005ldlar\006ldlarb\006ldlarh\006ldnf1b\006"
16008 …{ 2495 /* ldff1w */, AArch64::LDFF1W_REAL, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg…
16009 …{ 2495 /* ldff1w */, AArch64::GLDFF1W_IMM_REAL, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1…
16010 …{ 2495 /* ldff1w */, AArch64::LDFF1W_D_REAL, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__R…
16011 …{ 2495 /* ldff1w */, AArch64::GLDFF1W_D_IMM_REAL, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1…
16012 …{ 2495 /* ldff1w */, AArch64::LDFF1W_REAL, Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__…
16013 …{ 2495 /* ldff1w */, AArch64::GLDFF1W_IMM_REAL, Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg…
16014 …{ 2495 /* ldff1w */, AArch64::LDFF1W_D_REAL, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1…
16015 …{ 2495 /* ldff1w */, AArch64::GLDFF1W_D_IMM_REAL, Convert__SVEVectorList1641_0__SVEPredicate3bAnyR…
16016 …{ 2495 /* ldff1w */, AArch64::LDFF1W_REAL, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg…
[all …]
DAArch64GenAsmWriter.inc22238 /* 2310 */ "ldff1w $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0"
22239 /* 2338 */ "ldff1w $\xFF\x01\x21, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0"
22462 /* 6821 */ "ldff1w $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0"
22463 /* 6847 */ "ldff1w $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]\0"
DAArch64GenAsmWriter1.inc22959 /* 2310 */ "ldff1w $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0"
22960 /* 2338 */ "ldff1w $\xFF\x01\x21, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0"
23183 /* 6813 */ "ldff1w $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0"
23184 /* 6839 */ "ldff1w $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]\0"
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64SVEInstrInfo.td434 defm LDFF1W : sve_mem_cldff_ss<0b1010, "ldff1w", Z_s, ZPR32, GPR64shifted32>;
435 defm LDFF1W_D : sve_mem_cldff_ss<0b1011, "ldff1w", Z_d, ZPR64, GPR64shifted32>;
480 …defm GLDFF1W : sve_mem_32b_gld_vs_32_unscaled<0b1011, "ldff1w", null_frag, nul…
489 …defm GLDFF1W : sve_mem_32b_gld_sv_32_scaled<0b1011, "ldff1w", null_frag, …
502 …defm GLDFF1W : sve_mem_32b_gld_vi_32_ptrs<0b1011, "ldff1w", uimm5s4, null_frag, …
517 …defm GLDFF1W_D : sve_mem_64b_gld_vi_64_ptrs<0b1011, "ldff1w", uimm5s4, null_frag, …
534 …defm GLDFF1W_D : sve_mem_64b_gld_vs2_64_unscaled<0b1011, "ldff1w", null_frag, nxv2i32>;
547 …defm GLDFF1W_D : sve_mem_64b_gld_sv2_64_scaled<0b1011, "ldff1w", null_frag, ZP…
564 …defm GLDFF1W_D : sve_mem_64b_gld_vs_32_unscaled<0b1011, "ldff1w", null_frag, nul…
577 …defm GLDFF1W_D : sve_mem_64b_gld_sv_32_scaled<0b1011, "ldff1w", null_frag, null_frag, …
/external/vixl/test/aarch64/
Dtest-assembler-sve-aarch64.cc9110 Ld1Macro ldff1w = &MacroAssembler::Ldff1w; in TEST_SVE() local
9112 ldff1_scaled_offset_helper(kSRegSize, kSRegSize, ldff1w, ld1w); in TEST_SVE()
9113 ldff1_scaled_offset_helper(kSRegSize, kDRegSize, ldff1w, ld1w); in TEST_SVE()
9148 Ld1Macro ldff1w = &MacroAssembler::Ldff1w; in sve_ldff1_scalar_plus_vector_32_scaled_offset() local
9150 ldff1_32_scaled_offset_helper(kSRegSize, ldff1w, ld1w, UXTW); in sve_ldff1_scalar_plus_vector_32_scaled_offset()
9151 ldff1_32_scaled_offset_helper(kSRegSize, ldff1w, ld1w, SXTW); in sve_ldff1_scalar_plus_vector_32_scaled_offset()
9182 Ld1Macro ldff1w = &MacroAssembler::Ldff1w; in sve_ldff1_scalar_plus_vector_32_unscaled_offset() local
9184 ldff1_32_unscaled_offset_helper(kSRegSize, ldff1w, ld1w, UXTW); in sve_ldff1_scalar_plus_vector_32_unscaled_offset()
9185 ldff1_32_unscaled_offset_helper(kSRegSize, ldff1w, ld1w, SXTW); in sve_ldff1_scalar_plus_vector_32_unscaled_offset()
9217 Ld1Macro ldff1w = &MacroAssembler::Ldff1w; in sve_ldff1_scalar_plus_vector_32_unpacked_scaled_offset() local
[all …]
Dtest-disasm-sve-aarch64.cc3423 COMPARE_PREFIX(ldff1w(z12.VnS(), in TEST()
3442 COMPARE_PREFIX(ldff1w(z5.VnS(), in TEST()
3535 COMPARE_PREFIX(ldff1w(z26.VnD(), p6.Zeroing(), SVEMemOperand(z15.VnD(), 4)), in TEST()
3834 COMPARE_PREFIX(ldff1w(z12.VnD(), p3.Zeroing(), SVEMemOperand(x25, z27.VnD())), in TEST()
3854 COMPARE_PREFIX(ldff1w(z5.VnD(), in TEST()
3880 COMPARE_PREFIX(ldff1w(z22.VnD(), in TEST()
3906 COMPARE_PREFIX(ldff1w(z5.VnD(), in TEST()
4433 COMPARE_PREFIX(ldff1w(z11.VnS(), p7.Zeroing(), SVEMemOperand(sp)), in TEST()
4435 COMPARE_PREFIX(ldff1w(z6.VnD(), p6.Zeroing(), SVEMemOperand(x5, x0, LSL, 2)), in TEST()
/external/llvm-project/llvm/lib/Target/AArch64/
DAArch64SVEInstrInfo.td774 defm LDFF1W : sve_mem_cldff_ss<0b1010, "ldff1w", Z_s, ZPR32, GPR64shifted32>;
775 defm LDFF1W_D : sve_mem_cldff_ss<0b1011, "ldff1w", Z_d, ZPR64, GPR64shifted32>;
820 …defm GLDFF1W : sve_mem_32b_gld_vs_32_unscaled<0b1011, "ldff1w", AArch64ldff1_gather_sxtw_z, A…
829 …defm GLDFF1W : sve_mem_32b_gld_sv_32_scaled<0b1011, "ldff1w", AArch64ldff1_gather_sxtw_scaled_…
842 …defm GLDFF1W : sve_mem_32b_gld_vi_32_ptrs<0b1011, "ldff1w", uimm5s4, AArch64ldff1_gather_imm_z…
857 …defm GLDFF1W_D : sve_mem_64b_gld_vi_64_ptrs<0b1011, "ldff1w", uimm5s4, AArch64ldff1_gather_imm_z…
874 …defm GLDFF1W_D : sve_mem_64b_gld_vs2_64_unscaled<0b1011, "ldff1w", AArch64ldff1_gather_z, nxv2i…
887 …defm GLDFF1W_D : sve_mem_64b_gld_sv2_64_scaled<0b1011, "ldff1w", AArch64ldff1_gather_scaled_z, …
904 …defm GLDFF1W_D : sve_mem_64b_gld_vs_32_unscaled<0b1011, "ldff1w", AArch64ldff1_gather_sxtw_z, A…
917 …defm GLDFF1W_D : sve_mem_64b_gld_sv_32_scaled<0b1011, "ldff1w", AArch64ldff1_gather_sxtw_scaled_…
/external/vixl/src/aarch64/
Dmacro-assembler-sve-aarch64.cc1429 static_cast<SVELoad1Fn>(&Assembler::ldff1w)); in Ldff1w()
Dassembler-aarch64.h4714 void ldff1w(const ZRegister& zt,
4811 void ldff1w(const ZRegister& zt,
4817 void ldff1w(const ZRegister& zt,
Dassembler-sve-aarch64.cc4442 void Assembler::ldff1w(const ZRegister& zt, in ldff1w() function in vixl::aarch64::Assembler
4459 void Assembler::ldff1w(const ZRegister& zt, in ldff1w() function in vixl::aarch64::Assembler
Dmacro-assembler-aarch64.h5135 ldff1w(zt, pg, xn, zm); in Ldff1w()
5143 ldff1w(zt, pg, zn, imm5); in Ldff1w()