| /external/llvm-project/llvm/test/MC/AArch64/SVE2/ |
| D | ldnt1d-diagnostics.s | 7 ldnt1d { z0.b }, p0/z, [z0.s] label
12 ldnt1d { z0.h }, p0/z, [z0.s] label
17 ldnt1d { z0.s }, p0/z, [z0.s] label
26 ldnt1d { z0.d }, p0/z, [z0.b] label
35 ldnt1d { z0.d }, p0/z, [z0.d, z1.d] label
44 ldnt1d { z0.d }, p0/m, [z0.d] label
53 ldnt1d { z27.d }, p8/z, [z0.d] label
62 ldnt1d { }, p0/z, [z0.d] label
67 ldnt1d { z0.d, z1.d }, p0/z, [z0.d] label
72 ldnt1d { v0.2d }, p0/z, [z0.d] label
[all …]
|
| D | ldnt1d.s | 10 ldnt1d z0.d, p0/z, [z1.d] label
16 ldnt1d z31.d, p7/z, [z31.d, xzr] label
22 ldnt1d z31.d, p7/z, [z31.d, x0] label
28 ldnt1d { z0.d }, p0/z, [z1.d] label
34 ldnt1d { z31.d }, p7/z, [z31.d, xzr] label
40 ldnt1d { z31.d }, p7/z, [z31.d, x0] label
|
| /external/llvm-project/llvm/test/MC/AArch64/SVE/ |
| D | ldnt1d-diagnostics.s | 6 ldnt1d z23.d, p0/z, [x13, #-9, MUL VL] label
11 ldnt1d z29.d, p0/z, [x3, #8, MUL VL] label
20 ldnt1d z0.b, p0/z, [x0] label
25 ldnt1d z0.h, p0/z, [x0] label
30 ldnt1d z0.s, p0/z, [x0] label
39 ldnt1d z27.d, p8/z, [x0] label
48 ldnt1d { }, p0/z, [x1, #1, MUL VL] label
53 ldnt1d { z1.d, z2.d }, p0/z, [x1, #1, MUL VL] label
58 ldnt1d { v0.2d }, p0/z, [x1, #1, MUL VL] label
68 ldnt1d { z0.d }, p0/z, [x0, x0, lsl #3] label
[all …]
|
| D | ldnt1d.s | 10 ldnt1d z0.d, p0/z, [x0] label
16 ldnt1d { z0.d }, p0/z, [x0] label
22 ldnt1d { z23.d }, p3/z, [x13, #-8, mul vl] label
28 ldnt1d { z21.d }, p5/z, [x10, #7, mul vl] label
34 ldnt1d { z0.d }, p0/z, [x0, x0, lsl #3] label
|
| /external/llvm-project/llvm/test/CodeGen/AArch64/ |
| D | sve2-intrinsics-nt-gather-loads-64bit-scaled-offset.ll | 41 ; CHECK-NEXT: ldnt1d { z0.d }, p0/z, [z0.d, x0]
52 ; CHECK-NEXT: ldnt1d { z0.d }, p0/z, [z0.d, x0]
|
| D | sve2-intrinsics-nt-gather-loads-64bit-unscaled-offset.ll | 47 ; CHECK: ldnt1d { z0.d }, p0/z, [z0.d, x0]
57 ; CHECK: ldnt1d { z0.d }, p0/z, [z0.d, x0]
|
| D | sve-pred-non-temporal-ldst-addressing-mode-reg-imm.ll | 16 ; CHECK-NEXT: ldnt1d { z[[DATA:[0-9]+]].d }, p0/z, [x{{[0-9]+}}]
38 ; CHECK-NEXT: ldnt1d { z[[DATA:[0-9]+]].d }, p0/z, [x0, #-8, mul vl]
55 ; CHECK-NEXT: ldnt1d { z[[DATA:[0-9]+]].d }, p0/z, [x0, #-6, mul vl]
|
| D | sve-pred-non-temporal-ldst-addressing-mode-reg-reg.ll | 11 ; CHECK-NEXT: ldnt1d { z[[DATA:[0-9]+]].d }, p0/z, [x0, x1, lsl #3]
25 ; CHECK-NEXT: ldnt1d { z[[DATA:[0-9]+]].d }, p0/z, [x0, x1, lsl #3]
|
| D | sve2-intrinsics-nt-gather-loads-vector-base-scalar-offset.ll | 93 ; CHECK: ldnt1d { z0.d }, p0/z, [z0.d, x0]
104 ; CHECK: ldnt1d { z0.d }, p0/z, [z0.d, x0]
|
| D | sve-intrinsics-loads.ll | 269 ; CHECK: ldnt1d { z0.d }, p0/z, [x0]
278 ; CHECK: ldnt1d { z0.d }, p0/z, [x0]
|
| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/ |
| D | AArch64GenAsmMatcher.inc | 12528 "ldnt1b\006ldnt1d\006ldnt1h\007ldnt1sb\007ldnt1sh\007ldnt1sw\006ldnt1w\003"
16139 …{ 2595 /* ldnt1d */, AArch64::LDNT1D_ZRI, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1…
16140 …{ 2595 /* ldnt1d */, AArch64::LDNT1D_ZZR_D_REAL, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_…
16141 …{ 2595 /* ldnt1d */, AArch64::LDNT1D_ZRI, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__R…
16142 …{ 2595 /* ldnt1d */, AArch64::LDNT1D_ZZR_D_REAL, Convert__SVEVectorList1641_0__SVEPredicate3bAnyRe…
16143 …{ 2595 /* ldnt1d */, AArch64::LDNT1D_ZRR, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1…
16144 …{ 2595 /* ldnt1d */, AArch64::LDNT1D_ZZR_D_REAL, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_…
16145 …{ 2595 /* ldnt1d */, AArch64::LDNT1D_ZRR, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__R…
16146 …{ 2595 /* ldnt1d */, AArch64::LDNT1D_ZZR_D_REAL, Convert__SVEVectorList1641_0__SVEPredicate3bAnyRe…
16147 …{ 2595 /* ldnt1d */, AArch64::LDNT1D_ZRI, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1…
[all …]
|
| D | AArch64GenAsmWriter.inc | 22485 /* 7408 */ "ldnt1d $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0"
22486 /* 7434 */ "ldnt1d $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0"
|
| D | AArch64GenAsmWriter1.inc | 23206 /* 7400 */ "ldnt1d $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0"
23207 /* 7426 */ "ldnt1d $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0"
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64SVEInstrInfo.td | 585 defm LDNT1D_ZRI : sve_mem_cldnt_si<0b11, "ldnt1d", Z_d, ZPR64>;
591 defm LDNT1D_ZRR : sve_mem_cldnt_ss<0b11, "ldnt1d", Z_d, ZPR64, GPR64NoXZRshifted64>;
1571 defm LDNT1D_ZZR_D : sve2_mem_gldnt_vs<0b11110, "ldnt1d", Z_d, ZPR64>;
|
| /external/vixl/src/aarch64/ |
| D | macro-assembler-sve-aarch64.cc | 1552 &MacroAssembler::ldnt1d, in Ldnt1d()
|
| D | assembler-aarch64.h | 4874 void ldnt1d(const ZRegister& zt,
|
| D | assembler-sve-aarch64.cc | 4941 void Assembler::ldnt1d(const ZRegister& zt, in ldnt1d() function in vixl::aarch64::Assembler
|
| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64SVEInstrInfo.td | 925 defm LDNT1D_ZRI : sve_mem_cldnt_si<0b11, "ldnt1d", Z_d, ZPR64>;
931 defm LDNT1D_ZRR : sve_mem_cldnt_ss<0b11, "ldnt1d", Z_d, ZPR64, GPR64NoXZRshifted64>;
2750 …defm LDNT1D_ZZR_D : sve2_mem_gldnt_vs_64_ptrs<0b11110, "ldnt1d", AArch64ldnt1_gather_z, nxv2i64…
|
| /external/vixl/test/aarch64/ |
| D | test-disasm-sve-aarch64.cc | 4498 COMPARE_PREFIX(ldnt1d(z10.VnD(), in TEST()
4517 COMPARE_PREFIX(ldnt1d(z2.VnD(), in TEST()
|