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Searched refs:ldnt1h (Results 1 – 20 of 20) sorted by relevance

/external/llvm-project/llvm/test/MC/AArch64/SVE2/
Dldnt1h.s10 ldnt1h z0.s, p0/z, [z1.s] label
16 ldnt1h z31.s, p7/z, [z31.s, xzr] label
22 ldnt1h z31.s, p7/z, [z31.s, x0] label
28 ldnt1h z0.d, p0/z, [z1.d] label
34 ldnt1h z31.d, p7/z, [z31.d, xzr] label
40 ldnt1h z31.d, p7/z, [z31.d, x0] label
46 ldnt1h { z0.s }, p0/z, [z1.s] label
52 ldnt1h { z31.s }, p7/z, [z31.s, xzr] label
58 ldnt1h { z31.s }, p7/z, [z31.s, x0] label
64 ldnt1h { z0.d }, p0/z, [z1.d] label
[all …]
Dldnt1h-diagnostics.s7 ldnt1h { z0.b }, p0/z, [z0.s] label
12 ldnt1h { z0.h }, p0/z, [z0.s] label
21 ldnt1h { z0.s }, p0/z, [z0.b] label
26 ldnt1h { z0.d }, p0/z, [z0.h] label
35 ldnt1h { z0.d }, p0/z, [z0.d, z1.d] label
44 ldnt1h { z0.d }, p0/m, [z0.d] label
53 ldnt1h { z27.d }, p8/z, [z0.d] label
62 ldnt1h { }, p0/z, [z0.d] label
67 ldnt1h { z0.d, z1.d }, p0/z, [z0.d] label
72 ldnt1h { v0.2d }, p0/z, [z0.d] label
[all …]
/external/llvm-project/llvm/test/MC/AArch64/SVE/
Dldnt1h-diagnostics.s6 ldnt1h z23.h, p0/z, [x13, #-9, MUL VL] label
11 ldnt1h z29.h, p0/z, [x3, #8, MUL VL] label
20 ldnt1h z0.b, p0/z, [x0] label
25 ldnt1h z0.s, p0/z, [x0] label
30 ldnt1h z0.d, p0/z, [x0] label
39 ldnt1h z27.h, p8/z, [x0] label
48 ldnt1h { }, p0/z, [x1, #1, MUL VL] label
53 ldnt1h { z1.h, z2.h }, p0/z, [x1, #1, MUL VL] label
58 ldnt1h { v0.2d }, p0/z, [x1, #1, MUL VL] label
68 ldnt1h { z0.h }, p0/z, [x0, x0, lsl #1] label
[all …]
Dldnt1h.s10 ldnt1h z0.h, p0/z, [x0] label
16 ldnt1h { z0.h }, p0/z, [x0] label
22 ldnt1h { z23.h }, p3/z, [x13, #-8, mul vl] label
28 ldnt1h { z21.h }, p5/z, [x10, #7, mul vl] label
34 ldnt1h { z0.h }, p0/z, [x0, x0, lsl #1] label
/external/llvm-project/llvm/test/CodeGen/AArch64/
Dsve-pred-non-temporal-ldst-addressing-mode-reg-reg.ll72 ; CHECK-NEXT: ldnt1h { z[[DATA:[0-9]+]].h }, p0/z, [x0, x1, lsl #1]
86 ; CHECK-NEXT: ldnt1h { z[[DATA:[0-9]+]].h }, p0/z, [x0, x1, lsl #1]
100 ; CHECK-NEXT: ldnt1h { z[[DATA:[0-9]+]].h }, p0/z, [x0, x1, lsl #1]
Dsve2-intrinsics-nt-gather-loads-64bit-scaled-offset.ll11 ; ldnt1h z0.d, p0/z, [z0.d, x0]
17 ; CHECK-NEXT: ldnt1h { z0.d }, p0/z, [z0.d, x0]
Dsve2-intrinsics-nt-gather-loads-32bit-unscaled-offset.ll10 ; e.g. ldnt1h { z0.s }, p0/z, [z0.s, x0]
28 ; CHECK: ldnt1h { z0.s }, p0/z, [z0.s, x0]
Dsve2-intrinsics-nt-gather-loads-64bit-unscaled-offset.ll9 ; e.g. ldnt1h { z0.d }, p0/z, [z0.d, x0]
25 ; CHECK: ldnt1h { z0.d }, p0/z, [z0.d, x0]
Dsve-pred-non-temporal-ldst-addressing-mode-reg-imm.ll111 ; CHECK-NEXT: ldnt1h { z[[DATA:[0-9]+]].h }, p0/z, [x0, #6, mul vl]
128 ; CHECK-NEXT: ldnt1h { z[[DATA:[0-9]+]].h }, p0/z, [x0, #-1, mul vl]
145 ; CHECK-NEXT: ldnt1h { z[[DATA:[0-9]+]].h }, p0/z, [x0, #-1, mul vl]
Dsve2-intrinsics-nt-gather-loads-vector-base-scalar-offset.ll38 ; CHECK: ldnt1h { z0.s }, p0/z, [z0.s, x0]
49 ; CHECK: ldnt1h { z0.d }, p0/z, [z0.d, x0]
Dsve-intrinsics-loads.ll216 ; CHECK: ldnt1h { z0.h }, p0/z, [x0]
225 ; CHECK: ldnt1h { z0.h }, p0/z, [x0]
234 ; CHECK: ldnt1h { z0.h }, p0/z, [x0]
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/
DAArch64GenAsmMatcher.inc12528 "ldnt1b\006ldnt1d\006ldnt1h\007ldnt1sb\007ldnt1sh\007ldnt1sw\006ldnt1w\003"
16149 …{ 2602 /* ldnt1h */, AArch64::LDNT1H_ZRI, Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Reg1…
16150 …{ 2602 /* ldnt1h */, AArch64::LDNT1H_ZZR_S_REAL, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_…
16151 …{ 2602 /* ldnt1h */, AArch64::LDNT1H_ZZR_D_REAL, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_…
16152 …{ 2602 /* ldnt1h */, AArch64::LDNT1H_ZRI, Convert__SVEVectorList1161_0__SVEPredicate3bAnyReg1_1__R…
16153 …{ 2602 /* ldnt1h */, AArch64::LDNT1H_ZZR_S_REAL, Convert__SVEVectorList1321_0__SVEPredicate3bAnyRe…
16154 …{ 2602 /* ldnt1h */, AArch64::LDNT1H_ZZR_D_REAL, Convert__SVEVectorList1641_0__SVEPredicate3bAnyRe…
16155 …{ 2602 /* ldnt1h */, AArch64::LDNT1H_ZRR, Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Reg1…
16156 …{ 2602 /* ldnt1h */, AArch64::LDNT1H_ZZR_S_REAL, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_…
16157 …{ 2602 /* ldnt1h */, AArch64::LDNT1H_ZZR_D_REAL, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_…
[all …]
DAArch64GenAsmWriter.inc22487 /* 7462 */ "ldnt1h $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0"
22488 /* 7488 */ "ldnt1h $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0"
22489 /* 7516 */ "ldnt1h $\xFF\x01\x21, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0"
DAArch64GenAsmWriter1.inc23208 /* 7454 */ "ldnt1h $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0"
23209 /* 7480 */ "ldnt1h $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0"
23210 /* 7508 */ "ldnt1h $\xFF\x01\x21, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0"
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64SVEInstrInfo.td583 defm LDNT1H_ZRI : sve_mem_cldnt_si<0b01, "ldnt1h", Z_h, ZPR16>;
589 defm LDNT1H_ZRR : sve_mem_cldnt_ss<0b01, "ldnt1h", Z_h, ZPR16, GPR64NoXZRshifted16>;
1562 defm LDNT1H_ZZR_S : sve2_mem_gldnt_vs<0b00101, "ldnt1h", Z_s, ZPR32>;
1568 defm LDNT1H_ZZR_D : sve2_mem_gldnt_vs<0b10110, "ldnt1h", Z_d, ZPR64>;
/external/vixl/src/aarch64/
Dmacro-assembler-sve-aarch64.cc1565 &MacroAssembler::ldnt1h, in Ldnt1h()
Dassembler-aarch64.h4864 void ldnt1h(const ZRegister& zt,
Dassembler-sve-aarch64.cc4954 void Assembler::ldnt1h(const ZRegister& zt, in ldnt1h() function in vixl::aarch64::Assembler
/external/llvm-project/llvm/lib/Target/AArch64/
DAArch64SVEInstrInfo.td923 defm LDNT1H_ZRI : sve_mem_cldnt_si<0b01, "ldnt1h", Z_h, ZPR16>;
929 defm LDNT1H_ZRR : sve_mem_cldnt_ss<0b01, "ldnt1h", Z_h, ZPR16, GPR64NoXZRshifted16>;
2741 …defm LDNT1H_ZZR_S : sve2_mem_gldnt_vs_32_ptrs<0b00101, "ldnt1h", AArch64ldnt1_gather_z, nxv4i16…
2747 …defm LDNT1H_ZZR_D : sve2_mem_gldnt_vs_64_ptrs<0b10110, "ldnt1h", AArch64ldnt1_gather_z, nxv2i16…
/external/vixl/test/aarch64/
Dtest-disasm-sve-aarch64.cc4502 COMPARE_PREFIX(ldnt1h(z30.VnH(), in TEST()
4521 COMPARE_PREFIX(ldnt1h(z26.VnH(), in TEST()