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Searched refs:ldnt1w (Results 1 – 20 of 20) sorted by relevance

/external/llvm-project/llvm/test/MC/AArch64/SVE2/
Dldnt1w.s10 ldnt1w z0.s, p0/z, [z1.s] label
16 ldnt1w z31.s, p7/z, [z31.s, xzr] label
22 ldnt1w z31.s, p7/z, [z31.s, x0] label
28 ldnt1w z0.d, p0/z, [z1.d] label
34 ldnt1w z31.d, p7/z, [z31.d, xzr] label
40 ldnt1w z31.d, p7/z, [z31.d, x0] label
46 ldnt1w { z0.s }, p0/z, [z1.s] label
52 ldnt1w { z31.s }, p7/z, [z31.s, xzr] label
58 ldnt1w { z31.s }, p7/z, [z31.s, x0] label
64 ldnt1w { z0.d }, p0/z, [z1.d] label
[all …]
Dldnt1w-diagnostics.s7 ldnt1w { z0.b }, p0/z, [z0.s] label
12 ldnt1w { z0.h }, p0/z, [z0.s] label
21 ldnt1w { z0.s }, p0/z, [z0.b] label
26 ldnt1w { z0.d }, p0/z, [z0.h] label
35 ldnt1w { z0.d }, p0/z, [z0.d, z1.d] label
44 ldnt1w { z0.d }, p0/m, [z0.d] label
53 ldnt1w { z27.d }, p8/z, [z0.d] label
62 ldnt1w { }, p0/z, [z0.d] label
67 ldnt1w { z0.d, z1.d }, p0/z, [z0.d] label
72 ldnt1w { v0.2d }, p0/z, [z0.d] label
[all …]
/external/llvm-project/llvm/test/MC/AArch64/SVE/
Dldnt1w-diagnostics.s6 ldnt1w z23.s, p0/z, [x13, #-9, MUL VL] label
11 ldnt1w z29.s, p0/z, [x3, #8, MUL VL] label
20 ldnt1w z0.b, p0/z, [x0] label
25 ldnt1w z0.h, p0/z, [x0] label
30 ldnt1w z0.d, p0/z, [x0] label
39 ldnt1w z27.s, p8/z, [x0] label
48 ldnt1w { }, p0/z, [x1, #1, MUL VL] label
53 ldnt1w { z1.s, z2.s }, p0/z, [x1, #1, MUL VL] label
58 ldnt1w { v0.2d }, p0/z, [x1, #1, MUL VL] label
68 ldnt1w { z0.s }, p0/z, [x0, x0, lsl #2] label
[all …]
Dldnt1w.s10 ldnt1w z0.s, p0/z, [x0] label
16 ldnt1w { z0.s }, p0/z, [x0] label
22 ldnt1w { z23.s }, p3/z, [x13, #-8, mul vl] label
28 ldnt1w { z21.s }, p5/z, [x10, #7, mul vl] label
34 ldnt1w { z0.s }, p0/z, [x0, x0, lsl #2] label
/external/llvm-project/llvm/test/CodeGen/AArch64/
Dsve2-intrinsics-nt-gather-loads-32bit-unscaled-offset.ll40 ; CHECK: ldnt1w { z0.s }, p0/z, [z0.s, x0]
50 ; CHECK: ldnt1w { z0.s }, p0/z, [z0.s, x0]
Dsve2-intrinsics-nt-gather-loads-vector-base-scalar-offset.ll61 ; CHECK: ldnt1w { z0.s }, p0/z, [z0.s, x0]
71 ; CHECK: ldnt1w { z0.s }, p0/z, [z0.s, x0]
81 ; CHECK: ldnt1w { z0.d }, p0/z, [z0.d, x0]
Dsve-pred-non-temporal-ldst-addressing-mode-reg-reg.ll41 ; CHECK-NEXT: ldnt1w { z[[DATA:[0-9]+]].s }, p0/z, [x0, x1, lsl #2]
55 ; CHECK-NEXT: ldnt1w { z[[DATA:[0-9]+]].s }, p0/z, [x0, x1, lsl #2]
Dsve2-intrinsics-nt-gather-loads-64bit-scaled-offset.ll29 ; CHECK-NEXT: ldnt1w { z0.d }, p0/z, [z0.d, x0]
Dsve-pred-non-temporal-ldst-addressing-mode-reg-imm.ll74 ; CHECK-NEXT: ldnt1w { z[[DATA:[0-9]+]].s }, p0/z, [x0, #6, mul vl]
91 ; CHECK-NEXT: ldnt1w { z[[DATA:[0-9]+]].s }, p0/z, [x0, #-1, mul vl]
Dsve2-intrinsics-nt-gather-loads-64bit-unscaled-offset.ll36 ; CHECK: ldnt1w { z0.d }, p0/z, [z0.d, x0]
Dsve-intrinsics-loads.ll247 ; CHECK: ldnt1w { z0.s }, p0/z, [x0]
256 ; CHECK: ldnt1w { z0.s }, p0/z, [x0]
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/
DAArch64GenAsmMatcher.inc12528 "ldnt1b\006ldnt1d\006ldnt1h\007ldnt1sb\007ldnt1sh\007ldnt1sw\006ldnt1w\003"
16183 …{ 2633 /* ldnt1w */, AArch64::LDNT1W_ZRI, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1…
16184 …{ 2633 /* ldnt1w */, AArch64::LDNT1W_ZZR_S_REAL, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_…
16185 …{ 2633 /* ldnt1w */, AArch64::LDNT1W_ZZR_D_REAL, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_…
16186 …{ 2633 /* ldnt1w */, AArch64::LDNT1W_ZRI, Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__R…
16187 …{ 2633 /* ldnt1w */, AArch64::LDNT1W_ZZR_S_REAL, Convert__SVEVectorList1321_0__SVEPredicate3bAnyRe…
16188 …{ 2633 /* ldnt1w */, AArch64::LDNT1W_ZZR_D_REAL, Convert__SVEVectorList1641_0__SVEPredicate3bAnyRe…
16189 …{ 2633 /* ldnt1w */, AArch64::LDNT1W_ZRR, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1…
16190 …{ 2633 /* ldnt1w */, AArch64::LDNT1W_ZZR_S_REAL, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_…
16191 …{ 2633 /* ldnt1w */, AArch64::LDNT1W_ZZR_D_REAL, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_…
[all …]
DAArch64GenAsmWriter.inc22495 /* 7689 */ "ldnt1w $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]\0"
22496 /* 7715 */ "ldnt1w $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0"
22497 /* 7743 */ "ldnt1w $\xFF\x01\x21, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0"
DAArch64GenAsmWriter1.inc23216 /* 7681 */ "ldnt1w $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]\0"
23217 /* 7707 */ "ldnt1w $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0"
23218 /* 7735 */ "ldnt1w $\xFF\x01\x21, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0"
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64SVEInstrInfo.td584 defm LDNT1W_ZRI : sve_mem_cldnt_si<0b10, "ldnt1w", Z_s, ZPR32>;
590 defm LDNT1W_ZRR : sve_mem_cldnt_ss<0b10, "ldnt1w", Z_s, ZPR32, GPR64NoXZRshifted32>;
1563 defm LDNT1W_ZZR_S : sve2_mem_gldnt_vs<0b01001, "ldnt1w", Z_s, ZPR32>;
1570 defm LDNT1W_ZZR_D : sve2_mem_gldnt_vs<0b11010, "ldnt1w", Z_d, ZPR64>;
/external/vixl/src/aarch64/
Dmacro-assembler-sve-aarch64.cc1578 &MacroAssembler::ldnt1w, in Ldnt1w()
Dassembler-aarch64.h4869 void ldnt1w(const ZRegister& zt,
Dassembler-sve-aarch64.cc4967 void Assembler::ldnt1w(const ZRegister& zt, in ldnt1w() function in vixl::aarch64::Assembler
/external/llvm-project/llvm/lib/Target/AArch64/
DAArch64SVEInstrInfo.td924 defm LDNT1W_ZRI : sve_mem_cldnt_si<0b10, "ldnt1w", Z_s, ZPR32>;
930 defm LDNT1W_ZRR : sve_mem_cldnt_ss<0b10, "ldnt1w", Z_s, ZPR32, GPR64NoXZRshifted32>;
2742 …defm LDNT1W_ZZR_S : sve2_mem_gldnt_vs_32_ptrs<0b01001, "ldnt1w", AArch64ldnt1_gather_z, nxv4i32…
2749 …defm LDNT1W_ZZR_D : sve2_mem_gldnt_vs_64_ptrs<0b11010, "ldnt1w", AArch64ldnt1_gather_z, nxv2i32…
/external/vixl/test/aarch64/
Dtest-disasm-sve-aarch64.cc4506 COMPARE_PREFIX(ldnt1w(z0.VnS(), p4.Zeroing(), SVEMemOperand(x11, x1, LSL, 2)), in TEST()
4508 COMPARE_PREFIX(ldnt1w(z0.VnS(), p4.Zeroing(), SVEMemOperand(sp, xzr, LSL, 2)), in TEST()
4525 COMPARE_PREFIX(ldnt1w(z17.VnS(), in TEST()
4529 COMPARE_PREFIX(ldnt1w(z17.VnS(), in TEST()