| /external/llvm-project/llvm/test/CodeGen/AArch64/ |
| D | arm64-ldxr-stxr.ll | 39 ; CHECK: ldxrb w[[LOADVAL:[0-9]+]], [x0]
45 ; GISEL: ldxrb w[[LOADVAL:[0-9]+]], [x0]
|
| D | arm64_32-atomics.ll | 81 ; CHECK: ldxrb w0, [x0]
|
| D | atomic-ops.ll | 145 ; ; CHECK: ldxrb w[[OLD:[0-9]+]], [x[[ADDR]]]
261 ; ; CHECK: ldxrb w[[OLD:[0-9]+]], [x[[ADDR]]]
600 ; ; CHECK: ldxrb w[[OLD:[0-9]+]], [x[[ADDR]]]
1011 ; OUTLINE_ATOMICS-NEXT: ldxrb w8, [x9]
1025 ; CHECK: ldxrb w[[OLD:[0-9]+]], [x[[ADDR]]]
|
| D | atomic-ops-lse.ll | 3888 ; OUTLINE-ATOMICS-NEXT: ldxrb w10, [x9]
4048 ; OUTLINE-ATOMICS-NEXT: ldxrb w10, [x9]
4688 ; OUTLINE-ATOMICS-NEXT: ldxrb w10, [x9]
4848 ; OUTLINE-ATOMICS-NEXT: ldxrb w10, [x9]
7424 ; OUTLINE-ATOMICS-NEXT: ldxrb w8, [x9]
7582 ; OUTLINE-ATOMICS-NEXT: ldxrb w8, [x9]
8214 ; OUTLINE-ATOMICS-NEXT: ldxrb w8, [x9]
8372 ; OUTLINE-ATOMICS-NEXT: ldxrb w8, [x9]
|
| /external/llvm/test/MC/AArch64/ |
| D | arm64-memory.s | 458 ldxrb w6, [x1]
463 ; CHECK: ldxrb w6, [x1] ; encoding: [0x26,0x7c,0x5f,0x08]
|
| D | basic-a64-instructions.s | 2266 ldxrb w7, [x9]
|
| /external/llvm-project/llvm/test/MC/AArch64/ |
| D | arm64-memory.s | 458 ldxrb w6, [x1]
463 ; CHECK: ldxrb w6, [x1] ; encoding: [0x26,0x7c,0x5f,0x08]
|
| D | basic-a64-instructions.s | 2249 ldxrb w7, [x9]
|
| /external/llvm/test/CodeGen/AArch64/ |
| D | atomic-ops.ll | 103 ; ; CHECK: ldxrb w[[OLD:[0-9]+]], [x[[ADDR]]]
183 ; ; CHECK: ldxrb w[[OLD:[0-9]+]], [x[[ADDR]]]
423 ; ; CHECK: ldxrb w[[OLD:[0-9]+]], [x[[ADDR]]]
695 ; CHECK: ldxrb w[[OLD:[0-9]+]], [x[[ADDR]]]
|
| D | arm64-ldxr-stxr.ll | 37 ; CHECK: ldxrb w[[LOADVAL:[0-9]+]], [x0]
|
| /external/vixl/ |
| D | README.md | 124 `stxrb`, `stxrh`, `stxr`, `ldxrb`, `ldxrh`, `ldxr`, `stxp`, `ldxp`, `stlxrb`,
|
| /external/vixl/test/aarch64/ |
| D | test-disasm-aarch64.cc | 1567 COMPARE(ldxrb(w30, MemOperand(x0)), "ldxrb w30, [x0]"); in TEST()
1568 COMPARE(ldxrb(w1, MemOperand(sp)), "ldxrb w1, [sp]"); in TEST()
1569 COMPARE(ldxrb(x2, MemOperand(x3)), "ldxrb w2, [x3]"); in TEST()
1570 COMPARE(ldxrb(x4, MemOperand(sp)), "ldxrb w4, [sp]"); in TEST()
|
| D | test-trace-aarch64.cc | 227 __ ldxrb(w29, MemOperand(x0)); in GenerateTestSequenceBase() local
228 __ ldxrb(x2, MemOperand(x0)); in GenerateTestSequenceBase() local
|
| /external/llvm/test/MC/Disassembler/AArch64/ |
| D | arm64-memory.txt | 444 # CHECK: ldxrb w6, [x1]
|
| /external/llvm-project/llvm/test/MC/Disassembler/AArch64/ |
| D | arm64-memory.txt | 444 # CHECK: ldxrb w6, [x1]
|
| /external/llvm-project/llvm/test/tools/llvm-mca/AArch64/Cortex/ |
| D | A55-basic-instructions.s | 857 ldxrb w30, [x0] label
2114 # CHECK-NEXT: 1 3 1.00 * * U ldxrb w30, [x0]
3297 … - - - - - - - - - 1.00 - - ldxrb w30, [x0]
|
| /external/capstone/suite/MC/AArch64/ |
| D | basic-a64-instructions.s.cs | 880 0x27,0x7d,0x5f,0x08 = ldxrb w7, [x9]
|
| /external/vixl/test/test-trace-reference/ |
| D | log-disasm-colour | 171 0x~~~~~~~~~~~~~~~~ 085f7c1d ldxrb w29, [x0]
172 0x~~~~~~~~~~~~~~~~ 085f7c02 ldxrb w2, [x0]
|
| D | log-disasm | 171 0x~~~~~~~~~~~~~~~~ 085f7c1d ldxrb w29, [x0]
172 0x~~~~~~~~~~~~~~~~ 085f7c02 ldxrb w2, [x0]
|
| D | log-cpufeatures-custom | 171 0x~~~~~~~~~~~~~~~~ 085f7c1d ldxrb w29, [x0]
172 0x~~~~~~~~~~~~~~~~ 085f7c02 ldxrb w2, [x0]
|
| D | log-cpufeatures-colour | 171 0x~~~~~~~~~~~~~~~~ 085f7c1d ldxrb w29, [x0]
172 0x~~~~~~~~~~~~~~~~ 085f7c02 ldxrb w2, [x0]
|
| D | log-cpufeatures | 171 0x~~~~~~~~~~~~~~~~ 085f7c1d ldxrb w29, [x0]
172 0x~~~~~~~~~~~~~~~~ 085f7c02 ldxrb w2, [x0]
|
| /external/vixl/src/aarch64/ |
| D | assembler-aarch64.h | 1306 void ldxrb(const Register& rt, const MemOperand& src);
|
| D | assembler-aarch64.cc | 1427 void Assembler::ldxrb(const Register& rt, const MemOperand& src) { in ldxrb() function in vixl::aarch64::Assembler
|
| /external/vixl/doc/aarch64/ |
| D | supported-instructions-aarch64.md | 1861 void ldxrb(const Register& rt, const MemOperand& src)
|