| /external/llvm-project/llvm/test/CodeGen/AArch64/ |
| D | arm64-ldxr-stxr.ll | 58 ; CHECK: ldxrh w[[LOADVAL:[0-9]+]], [x0]
64 ; GISEL: ldxrh w[[LOADVAL:[0-9]+]], [x0]
|
| D | atomic-ops.ll | 174 ; ; CHECK: ldxrh w[[OLD:[0-9]+]], [x[[ADDR]]]
290 ; ; CHECK: ldxrh w[[OLD:[0-9]+]], [x[[ADDR]]]
404 ; ; CHECK: ldxrh w[[OLD:[0-9]+]], [x[[ADDR]]]
516 ; ; CHECK: ldxrh w[[OLD:[0-9]+]], [x[[ADDR]]]
739 ; OUTLINE_ATOMICS-NEXT: ldxrh w10, [x9]
754 ; CHECK: ldxrh w[[OLD:[0-9]+]], [x[[ADDR]]]
1201 ; OUTLINE_ATOMICS-NEXT: ldxrh w8, [x9]
1215 ; CHECK: ldxrh w[[OLD:[0-9]+]], [x[[ADDR]]]
|
| D | arm64_32-atomics.ll | 90 ; CHECK: ldxrh w0, [x0]
|
| D | atomic-ops-lse.ll | 3916 ; OUTLINE-ATOMICS-NEXT: ldxrh w10, [x9]
4076 ; OUTLINE-ATOMICS-NEXT: ldxrh w10, [x9]
4716 ; OUTLINE-ATOMICS-NEXT: ldxrh w10, [x9]
4876 ; OUTLINE-ATOMICS-NEXT: ldxrh w10, [x9]
7451 ; OUTLINE-ATOMICS-NEXT: ldxrh w8, [x9]
7609 ; OUTLINE-ATOMICS-NEXT: ldxrh w8, [x9]
8241 ; OUTLINE-ATOMICS-NEXT: ldxrh w8, [x9]
8399 ; OUTLINE-ATOMICS-NEXT: ldxrh w8, [x9]
|
| /external/llvm/test/CodeGen/AArch64/ |
| D | atomic-ops.ll | 123 ; ; CHECK: ldxrh w[[OLD:[0-9]+]], [x[[ADDR]]]
203 ; ; CHECK: ldxrh w[[OLD:[0-9]+]], [x[[ADDR]]]
283 ; ; CHECK: ldxrh w[[OLD:[0-9]+]], [x[[ADDR]]]
363 ; ; CHECK: ldxrh w[[OLD:[0-9]+]], [x[[ADDR]]]
524 ; CHECK: ldxrh w[[OLD:[0-9]+]], [x[[ADDR]]]
815 ; CHECK: ldxrh w[[OLD:[0-9]+]], [x[[ADDR]]]
|
| D | arm64-ldxr-stxr.ll | 51 ; CHECK: ldxrh w[[LOADVAL:[0-9]+]], [x0]
|
| /external/llvm/test/MC/AArch64/ |
| D | arm64-memory.s | 459 ldxrh w6, [x1]
464 ; CHECK: ldxrh w6, [x1] ; encoding: [0x26,0x7c,0x5f,0x48]
|
| D | basic-a64-instructions.s | 2267 ldxrh wzr, [x10]
|
| /external/llvm-project/llvm/test/MC/AArch64/ |
| D | arm64-memory.s | 459 ldxrh w6, [x1]
464 ; CHECK: ldxrh w6, [x1] ; encoding: [0x26,0x7c,0x5f,0x48]
|
| D | basic-a64-instructions.s | 2250 ldxrh wzr, [x10]
|
| /external/vixl/ |
| D | README.md | 124 `stxrb`, `stxrh`, `stxr`, `ldxrb`, `ldxrh`, `ldxr`, `stxp`, `ldxp`, `stlxrb`,
|
| /external/vixl/test/aarch64/ |
| D | test-disasm-aarch64.cc | 1571 COMPARE(ldxrh(w5, MemOperand(x6)), "ldxrh w5, [x6]"); in TEST()
1572 COMPARE(ldxrh(w7, MemOperand(sp)), "ldxrh w7, [sp]"); in TEST()
1573 COMPARE(ldxrh(x8, MemOperand(x9)), "ldxrh w8, [x9]"); in TEST()
1574 COMPARE(ldxrh(x10, MemOperand(sp)), "ldxrh w10, [sp]"); in TEST()
|
| D | test-trace-aarch64.cc | 229 __ ldxrh(w3, MemOperand(x0)); in GenerateTestSequenceBase() local
230 __ ldxrh(x4, MemOperand(x0)); in GenerateTestSequenceBase() local
|
| /external/llvm/test/MC/Disassembler/AArch64/ |
| D | arm64-memory.txt | 445 # CHECK: ldxrh w6, [x1]
|
| /external/llvm-project/llvm/test/MC/Disassembler/AArch64/ |
| D | arm64-memory.txt | 445 # CHECK: ldxrh w6, [x1]
|
| /external/llvm-project/llvm/test/tools/llvm-mca/AArch64/Cortex/ |
| D | A55-basic-instructions.s | 858 ldxrh w17, [x4] label
2115 # CHECK-NEXT: 1 3 1.00 * * U ldxrh w17, [x4]
3298 … - - - - - - - - - 1.00 - - ldxrh w17, [x4]
|
| /external/capstone/suite/MC/AArch64/ |
| D | basic-a64-instructions.s.cs | 881 0x5f,0x7d,0x5f,0x48 = ldxrh wzr, [x10]
|
| /external/vixl/test/test-trace-reference/ |
| D | log-disasm-colour | 173 0x~~~~~~~~~~~~~~~~ 485f7c03 ldxrh w3, [x0]
174 0x~~~~~~~~~~~~~~~~ 485f7c04 ldxrh w4, [x0]
|
| D | log-disasm | 173 0x~~~~~~~~~~~~~~~~ 485f7c03 ldxrh w3, [x0]
174 0x~~~~~~~~~~~~~~~~ 485f7c04 ldxrh w4, [x0]
|
| D | log-cpufeatures-custom | 173 0x~~~~~~~~~~~~~~~~ 485f7c03 ldxrh w3, [x0]
174 0x~~~~~~~~~~~~~~~~ 485f7c04 ldxrh w4, [x0]
|
| D | log-cpufeatures-colour | 173 0x~~~~~~~~~~~~~~~~ 485f7c03 ldxrh w3, [x0]
174 0x~~~~~~~~~~~~~~~~ 485f7c04 ldxrh w4, [x0]
|
| D | log-cpufeatures | 173 0x~~~~~~~~~~~~~~~~ 485f7c03 ldxrh w3, [x0]
174 0x~~~~~~~~~~~~~~~~ 485f7c04 ldxrh w4, [x0]
|
| /external/vixl/src/aarch64/ |
| D | assembler-aarch64.h | 1309 void ldxrh(const Register& rt, const MemOperand& src);
|
| D | assembler-aarch64.cc | 1433 void Assembler::ldxrh(const Register& rt, const MemOperand& src) { in ldxrh() function in vixl::aarch64::Assembler
|
| /external/vixl/doc/aarch64/ |
| D | supported-instructions-aarch64.md | 1868 void ldxrh(const Register& rt, const MemOperand& src)
|