| /external/mesa3d/src/intel/compiler/ |
| D | brw_vec4_live_variables.cpp | 158 BITSET_WORD new_liveout = (child_bd->livein[i] & in compute_live_variables()
178 if (new_livein & ~bd->livein[i]) { in compute_live_variables()
179 bd->livein[i] |= new_livein; in compute_live_variables()
205 if (BITSET_TEST(bd.livein, i)) { in compute_start_end()
238 block_data[i].livein = rzalloc_array(mem_ctx, BITSET_WORD, bitset_words); in vec4_live_variables()
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| D | brw_fs_live_variables.cpp | 170 BITSET_WORD new_liveout = (child_bd->livein[i] & in compute_live_variables()
190 if (new_livein & ~bd->livein[i]) { in compute_live_variables()
191 bd->livein[i] |= new_livein; in compute_live_variables()
239 BITSET_WORD livedefin = bd->livein[w] & bd->defin[w]; in compute_start_end()
298 block_data[i].livein = rzalloc_array(mem_ctx, BITSET_WORD, bitset_words); in fs_live_variables()
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| D | brw_fs_copy_propagation.cpp | 64 BITSET_WORD *livein; member
137 bd[block->num].livein = rzalloc_array(bd, BITSET_WORD, bitset_words); in fs_copy_prop_dataflow()
252 bd[block->num].livein[i] = 0u; in setup_initial_values()
258 bd[block->num].livein[i] = ~0u; in setup_initial_values()
299 bd[block->num].livein[i] = ~0u; in run()
308 bd[block->num].livein[i] &= (bd[parent->num].liveout[i] | in run()
319 bd[block->num].livein[i] &= livein_from_any_block; in run()
323 bd[block->num].copy[i] | (bd[block->num].livein[i] & in run()
346 fprintf(stderr, "%08x", bd[block->num].livein[i]); in dump_block_data()
1062 if (BITSET_TEST(dataflow.bd[block->num].livein, i)) { in opt_copy_propagation()
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| D | brw_schedule_instructions.cpp | 563 this->livein = ralloc_array(mem_ctx, BITSET_WORD *, block_count); in instruction_scheduler()
565 this->livein[i] = rzalloc_array(mem_ctx, BITSET_WORD, in instruction_scheduler()
585 this->livein = NULL; in instruction_scheduler()
647 BITSET_WORD **livein; member in instruction_scheduler
751 if (BITSET_TEST(live.block_data[block].livein, i)) { in setup_liveness()
753 if (!BITSET_TEST(livein[block], vgrf)) { in setup_liveness()
755 BITSET_SET(livein[block], vgrf); in setup_liveness()
772 if (!BITSET_TEST(livein[block + 1], i)) { in setup_liveness()
774 BITSET_SET(livein[block + 1], i); in setup_liveness()
832 if (!BITSET_TEST(livein[block_idx], inst->dst.nr) && in get_register_pressure_benefit()
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| D | brw_fs_live_variables.h | 57 BITSET_WORD *livein; member
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| D | brw_vec4_live_variables.h | 56 BITSET_WORD *livein; member
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| /external/llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/ |
| D | select-returnaddress-liveins.mir | 28 ; LR should be added as a livein to the entry block.
31 ; We should have lr as a livein to bb.0, and a copy from LR.
57 ; We should not have LR listed as a livein twice.
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| /external/mesa3d/src/freedreno/ir3/ |
| D | ir3_ra.c | 673 bd->livein = rzalloc_array(bd, BITSET_WORD, bitset_words); in ra_block_compute_live_ranges()
795 if (new_livein & ~bd->livein[i]) { in ra_compute_livein_liveout()
796 bd->livein[i] |= new_livein; in ra_compute_livein_liveout()
816 (succ_bd->livein[i] & ~bd->liveout[i]); in ra_compute_livein_liveout()
893 unsigned livein = 0; in ra_calc_block_live_values() local
894 BITSET_FOREACH_SET (name, bd->livein, ctx->alloc_count) { in ra_calc_block_live_values()
895 livein += name_size(ctx, name); in ra_calc_block_live_values()
900 d("block%u: LIVEIN: %u", block_id(block), livein); in ra_calc_block_live_values()
902 unsigned max = livein; in ra_calc_block_live_values()
1068 print_bitset(" l/i", bd->livein, ctx->alloc_count); in ra_add_interference()
[all …]
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| D | ir3_ra.h | 131 BITSET_WORD *livein; /* which defs reach entry point of block */ member
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| /external/llvm-project/llvm/test/DebugInfo/X86/ |
| D | live-debug-vars-discard-invalid.mir | 92 …; All DBG_VALUEs here should survive. %2 is livein as it was defined in bb.0, and it has use/def i…
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| /external/llvm-project/llvm/test/CodeGen/AMDGPU/ |
| D | regbank-reassign.mir | 148 # GCN-LABEL: livein{{$}}
151 name: livein
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| D | fold-immediate-operand-shrink.mir | 179 # This is not OK to clobber because vcc_lo has a livein use.
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| /external/llvm/test/CodeGen/ARM/ |
| D | 2012-05-29-TailDupBug.ll | 3 ; Teach taildup to update livein set to appease verifier.
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| /external/llvm-project/llvm/test/CodeGen/ARM/ |
| D | 2012-05-29-TailDupBug.ll | 3 ; Teach taildup to update livein set to appease verifier.
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| /external/llvm-project/llvm/test/CodeGen/AArch64/ |
| D | stp-opt-with-renaming.mir | 323 # The livein $q7 is killed early, so we can re-use it for renaming.
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| /external/llvm-project/llvm/docs/ |
| D | MIRLangRef.rst | 93 necessary for some passes that care about block livein lists.
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| /external/mesa3d/docs/relnotes/ |
| D | 20.0.0.rst | 2914 - freedreno/ir3/ra: remove ir print after livein/out
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