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Searched refs:loOperand (Results 1 – 8 of 8) sorted by relevance

/external/swiftshader/third_party/subzero/src/
DIcePhiLoweringImpl.h41 auto *DestLo = llvm::cast<Variable>(Target->loOperand(Dest)); in prelowerPhis32Bit()
49 PhiLo->addArgument(Target->loOperand(Src), Label); in prelowerPhis32Bit()
DIceTargetLoweringMIPS32.cpp2230 Operand *TargetMIPS32::loOperand(Operand *Operand) { in loOperand() function in Ice::MIPS32::TargetMIPS32
2454 auto *DestLo = llvm::cast<Variable>(loOperand(Dest)); in lowerInt64Arithmetic()
2466 Src0LoR = legalizeToReg(loOperand(Src0)); in lowerInt64Arithmetic()
2467 Src1LoR = legalizeToReg(loOperand(Src1)); in lowerInt64Arithmetic()
2481 Src0LoR = legalizeToReg(loOperand(Src0)); in lowerInt64Arithmetic()
2482 Src1LoR = legalizeToReg(loOperand(Src1)); in lowerInt64Arithmetic()
2493 Src0LoR = legalizeToReg(loOperand(Src0)); in lowerInt64Arithmetic()
2494 Src1LoR = legalizeToReg(loOperand(Src1)); in lowerInt64Arithmetic()
2508 Src0LoR = legalizeToReg(loOperand(Src0)); in lowerInt64Arithmetic()
2509 Src1LoR = legalizeToReg(loOperand(Src1)); in lowerInt64Arithmetic()
[all …]
DIceTargetLoweringARM32.cpp2090 Operand *TargetARM32::loOperand(Operand *Operand) { in loOperand() function in Ice::ARM32::TargetARM32
2563 div0Check(IceType_i64, loOperand(Src1), hiOperand(Src1)); in preambleDivRem()
2584 Int32Operands SrcsLo(loOperand(Src0), loOperand(Src1)); in lowerInt64Arithmetic()
2589 auto *DestLo = llvm::cast<Variable>(loOperand(Dest)); in lowerInt64Arithmetic()
3532 auto *DestLo = llvm::cast<Variable>(loOperand(Dest)); in lowerAssign()
3533 Operand *Src0Lo = legalize(loOperand(Src0), Legal_Reg | Legal_Flex); in lowerAssign()
3597 Src = loOperand(Src); in lowerInt1ForBranch()
3732 Operand *Lo = loOperand(Arg); in lowerCall()
3925 auto *DestLo = llvm::cast<Variable>(loOperand(Dest)); in lowerCast()
3977 auto *DestLo = llvm::cast<Variable>(loOperand(Dest)); in lowerCast()
[all …]
DIceTargetLoweringX86BaseImpl.h1433 TargetX86Base<TraitsType>::loOperand(Operand *Operand) {
2023 auto *DestLo = llvm::cast<Variable>(loOperand(Dest));
2025 Operand *Src0Lo = loOperand(Src0);
2027 Operand *Src1Lo = loOperand(Src1);
2926 auto *DestLo = llvm::cast<Variable>(loOperand(Dest));
2983 auto *DestLo = llvm::cast<Variable>(loOperand(Dest));
3030 Src0 = loOperand(Src0);
3039 Src0 = loOperand(Src0);
3229 SpillLo = loOperand(Src0RM);
3233 auto *DestLo = llvm::cast<Variable>(loOperand(Dest));
[all …]
DIceTargetLoweringX8632.cpp384 legalizeToReg(loOperand(Value), Traits::RegisterSet::Reg_eax); in moveReturnValueToRegister()
DIceTargetLoweringX86Base.h218 loOperand(Operand *Operand);
220 typename std::enable_if<T::Is64Bit, Operand>::type *loOperand(Operand *) { in loOperand() function
DIceTargetLoweringMIPS32.h711 Operand *loOperand(Operand *Operand);
DIceTargetLoweringARM32.h167 Operand *loOperand(Operand *Operand);