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/external/llvm-project/llvm/test/CodeGen/X86/
Dmisched-fusion.ll13 %var = phi i32* [ null, %entry ], [ %next.load, %loop1 ], [ %var, %loop2 ]
14 %next.ptr = phi i32** [ null, %entry ], [ %next.ptr, %loop1 ], [ %gep, %loop2 ]
15 br label %loop1
17 loop1:
22 loop2: ; preds = %loop1
30 ; CHECK: %loop1
38 %var = phi i32 [ 0, %entry ], [ %next.var, %loop1 ], [ %var2, %loop2 ]
39 %next.ptr = phi i32** [ null, %entry ], [ %next.ptr, %loop1 ], [ %gep, %loop2 ]
40 br label %loop1
42 loop1:
[all …]
/external/llvm/test/CodeGen/X86/
Dmisched-fusion.ll13 %var = phi i32* [ null, %entry ], [ %next.load, %loop1 ], [ %var, %loop2 ]
14 %next.ptr = phi i32** [ null, %entry ], [ %next.ptr, %loop1 ], [ %gep, %loop2 ]
15 br label %loop1
17 loop1:
22 loop2: ; preds = %loop1
30 ; CHECK: %loop1
38 %var = phi i32 [ 0, %entry ], [ %next.var, %loop1 ], [ %var2, %loop2 ]
39 %next.ptr = phi i32** [ null, %entry ], [ %next.ptr, %loop1 ], [ %gep, %loop2 ]
40 br label %loop1
42 loop1:
[all …]
/external/llvm-project/llvm/test/Analysis/ScalarEvolution/
Ddifferent-loops-recs.ll14 ; CHECK-NEXT: --> {14,+,3}<%loop1>
16 ; CHECK-NEXT: --> {20,+,6}<%loop1>
22 ; CHECK-NEXT: --> {{{{}}73,+,1}<%loop1>,+,1}<%loop2>
24 ; CHECK-NEXT: --> {{{{}}57,+,2}<%loop1>,+,2}<%loop2>
26 ; CHECK-NEXT: --> {{{{}}130,+,3}<%loop1>,+,3}<%loop2>
28 ; CHECK-NEXT: --> {{{{}}179,+,6}<%loop1>,+,6}<%loop2>
30 ; CHECK-NEXT: --> {{{{}}122,+,3}<%loop1>,+,3}<%loop2>
32 ; CHECK-NEXT: --> {{{{}}63,+,6}<%loop1>,+,3}<%loop2>
35 br label %loop1
37 loop1:
[all …]
/external/llvm-project/llvm/test/Transforms/IndVarSimplify/
Dpr39673.ll8 ; CHECK: loop1:
27 br label %loop1
29 loop1: ; preds = %entry, %loop1
30 %k1 = phi i16 [ 180, %entry ], [ %k1.add, %loop1 ]
31 %l1 = phi i16 [ 0, %entry ], [ %l1.add, %loop1 ]
35 br i1 %cmp1, label %loop1, label %loop2.preheader
37 loop2.preheader: ; preds = %loop1
38 %k1.add.lcssa = phi i16 [ %k1.add, %loop1 ]
59 ; CHECK: loop1:
79 br label %loop1
[all …]
/external/llvm-project/llvm/test/Analysis/PhiValues/
Dbasic.ll165 br i1 undef, label %loop1, label %loop2
167 loop1:
174 %phi1 = phi i32 [ 0, %entry ], [ %phi2, %loop1.then ], [ %phi3, %loop2.if ]
175 br i1 undef, label %loop1.if, label %loop1.else
177 loop1.if:
178 br i1 undef, label %loop1.then, label %loop2
180 loop1.else:
181 br label %loop1.then
183 loop1.then:
190 %phi2 = phi i32 [ 1, %loop1.if ], [ %phi1, %loop1.else ]
[all …]
/external/llvm-project/llvm/test/Transforms/LoopUnroll/
Druntime-loop4.ll9 ; EPILOG: loop1:
16 ; PROLOG: loop1:
22 br label %loop1
24 loop1:
25 %iv1 = phi i32 [ 0, %entry ], [ %inc1, %loop1.latch ]
43 br label %loop1.latch
45 loop1.latch:
48 br i1 %exitcnd1, label %exit, label %loop1
Dopt-levels.ll17 br label %loop1
19 loop1:
20 %iv1 = phi i32 [ 0, %entry ], [ %inc1, %loop1.latch ]
38 br label %loop1.latch
40 loop1.latch:
43 br i1 %exitcnd1, label %exit, label %loop1
/external/llvm/test/Transforms/LoopUnroll/
Druntime-loop4.ll9 ; EPILOG: loop1:
16 ; PROLOG: loop1:
22 br label %loop1
24 loop1:
25 %iv1 = phi i32 [ 0, %entry ], [ %inc1, %loop1.latch ]
43 br label %loop1.latch
45 loop1.latch:
48 br i1 %exitcnd1, label %exit, label %loop1
/external/llvm-project/llvm/test/Transforms/LoopVectorize/
Dpr30806.ll24 br i1 %cmp1, label %exit, label %loop1.preheader
26 ; Verify that a 'udiv' does not appear between the 'loop1.preheader' label, and
28 loop1.preheader:
29 ; CHECK-LABEL: loop1.preheader:
32 br label %loop1
34 loop1:
35 %outer_i = phi i32 [ %inc1, %loop2.exit ], [ 0, %loop1.preheader ]
61 br i1 %exitcond, label %exit, label %loop1
/external/llvm-project/llvm/test/Transforms/LoopReroll/
Dexternal_use.ll9 br label %loop1
11 loop1:
12 ;CHECK-LABEL: loop1:
13 ;CHECK-NEXT: %indvar = phi i64 [ 0, %entry ], [ %indvar.next, %loop1 ]
16 %indvar = phi i64 [ 0, %entry ], [ %indvar.next, %loop1 ]
20 br i1 %cmp, label %loop1, label %exit
23 %var1 = phi i64 [ %indvar.1, %loop1 ]
24 %var2 = phi i64 [ %indvar, %loop1 ]
/external/llvm/test/Transforms/LoopStrengthReduce/
Dhoist-parent-preheader.ll6 br i1 undef, label %loop1, label %return
8 loop1: ; preds = %bb13.loopexit, %entry
14 loop2: ; preds = %loop1, %loop2.backedge
15 %indvar414 = phi i64 [ %indvar.next415, %loop2.backedge ], [ 0, %loop1 ]
28 br i1 undef, label %loop1, label %return
Duglygep.ll70 br label %loop1
72 ; CHECK: loop1:
78 loop1: ; preds = %bb5, %bb0
86 bb2: ; preds = %loop1
91 ; CHECK-NEXT: br i1 true, label %[[BB5BB6:[^,]+]], label %loop1
94 br i1 true, label %bb6, label %loop1
118 bb6: ; preds = %bb5, %bb2, %loop1
119 %p8 = phi i32 [ %t0, %bb5 ], [ undef, %loop1 ], [ undef, %bb2 ] ; <i32> [#uses=0]
120 %p9 = phi i32 [ undef, %bb5 ], [ %i1, %loop1 ], [ %i1, %bb2 ] ; <i32> [#uses=0]
/external/llvm-project/llvm/test/Transforms/LoopStrengthReduce/
Dhoist-parent-preheader.ll6 br i1 undef, label %loop1, label %return
8 loop1: ; preds = %bb13.loopexit, %entry
14 loop2: ; preds = %loop1, %loop2.backedge
15 %indvar414 = phi i64 [ %indvar.next415, %loop2.backedge ], [ 0, %loop1 ]
28 br i1 undef, label %loop1, label %return
Duglygep.ll70 br label %loop1
72 ; CHECK: loop1:
78 loop1: ; preds = %bb5, %bb0
86 bb2: ; preds = %loop1
91 ; CHECK-NEXT: br i1 true, label %[[BB5BB6:[^,]+]], label %loop1
94 br i1 true, label %bb6, label %loop1
118 bb6: ; preds = %bb5, %bb2, %loop1
119 %p8 = phi i32 [ %t0, %bb5 ], [ undef, %loop1 ], [ undef, %bb2 ] ; <i32> [#uses=0]
120 %p9 = phi i32 [ undef, %bb5 ], [ %i1, %loop1 ], [ %i1, %bb2 ] ; <i32> [#uses=0]
/external/llvm-project/llvm/test/Transforms/LoopUnroll/AArch64/
Dpartial.ll31 br label %loop1
33 loop1:
34 %iv1 = phi i32 [ 0, %entry ], [ %inc1, %loop1.latch ]
47 br label %loop1.latch
49 loop1.latch:
52 br i1 %exitcnd2, label %exit, label %loop1
/external/ltp/utils/sctp/func_tests/
Dtest_autoclose.c65 sockaddr_storage_t loop1, loop2; in main() local
78 loop1.v4.sin_family = AF_INET; in main()
79 loop1.v4.sin_addr.s_addr = SCTP_IP_LOOPBACK; in main()
80 loop1.v4.sin_port = htons(SCTP_TESTPORT_1); in main()
95 test_bind(sk1, &loop1.sa, sizeof(loop1)); in main()
Dtest_fragments.c78 sockaddr_storage_t loop1; in main() local
107 loop1.v6.sin6_family = AF_INET6; in main()
108 loop1.v6.sin6_addr = in6addr_loopback; in main()
109 loop1.v6.sin6_port = htons(SCTP_TESTPORT_1); in main()
117 loop1.v4.sin_family = AF_INET; in main()
118 loop1.v4.sin_addr.s_addr = SCTP_IP_LOOPBACK; in main()
119 loop1.v4.sin_port = htons(SCTP_TESTPORT_1); in main()
135 test_bind(sk1, &loop1.sa, sizeof(loop1)); in main()
/external/llvm/test/Transforms/LoopUnroll/AArch64/
Dpartial.ll31 br label %loop1
33 loop1:
34 %iv1 = phi i32 [ 0, %entry ], [ %inc1, %loop1.latch ]
47 br label %loop1.latch
49 loop1.latch:
52 br i1 %exitcnd2, label %exit, label %loop1
/external/llvm-project/llvm/test/Transforms/InstCombine/
Dsimple_phi_condition.ll62 ; CHECK: loop1:
78 br label %loop1
80 loop1:
81 %iv1 = phi i32 [0, %if.true], [%iv1.next, %loop1]
84 br i1 %loop.cond.1, label %loop1, label %if.true.end
103 ; CHECK: loop1:
120 br label %loop1
122 loop1:
123 %iv1 = phi i32 [0, %if.true], [%iv1.next, %loop1]
126 br i1 %loop.cond.1, label %loop1, label %if.true.end
/external/llvm-project/llvm/test/Transforms/LoopSimplify/
Dpr28272.ll16 br label %loop1
18 loop1:
19 br i1 true, label %loop1, label %bb43
22 %a = phi i32 [ undef, %loop1 ], [ 0, %bb45 ], [ %a, %bb54 ]
23 %b = phi i32 [ 0, %loop1 ], [ 1, %bb54 ], [ %c, %bb45 ]
48 br label %loop1
50 loop1:
51 br i1 true, label %loop1, label %loop2.preheader
54 %a.ph = phi i32 [ undef, %loop1 ]
55 %b.ph = phi i32 [ 0, %loop1 ]
/external/llvm-project/polly/test/Isl/CodeGen/
Dsimple_vec_stride_one.ll9 br label %loop1
11 loop1:
12 %indvar = phi i64 [ %indvar.next, %loop1 ], [ 0, %bb3 ]
17 br i1 %cmp, label %loop1, label %loop2
20 %indvar.2 = phi i64 [ %indvar.2.next, %loop2 ], [ 0, %loop1 ]
/external/llvm-project/llvm/test/Transforms/IndVarSimplify/X86/
Dpr35406.ll10 ; CHECK: loop1:
39 br label %loop1
41 loop1: ; preds = %loop2.exit, %entry
49 general_case24: ; preds = %loop1
70 br i1 %i10, label %exit, label %loop1
72 exit: ; preds = %loop2.exit, %loop1
80 ; CHECK: loop1:
113 br label %loop1
115 loop1: ; preds = %loop2.exit, %entry
123 general_case24: ; preds = %loop1
[all …]
/external/llvm-project/llvm/test/Analysis/MemorySSA/
Dpr40749.ll16 br label %loop1
18 loop1:
23 %indvars.iv = phi i64 [ 0, %loop1 ], [ %indvars.iv.next, %loop6 ]
24 %phi18 = phi i32 [ %tmp0, %loop1 ], [ 0, %loop6 ]
25 %phi87 = phi i32 [ 0, %loop1 ], [ %tmp7, %loop6 ]
53 br label %loop1
/external/llvm-project/polly/test/Isl/CodeGen/MemAccess/
Dupdate_access_functions.ll5 ; CHECK-LABEL: polly.stmt.loop1:
26 br label %loop1
28 loop1:
29 %indvar = phi i64 [ %indvar.next, %loop1 ], [ 1, %bb3 ]
34 br i1 %cmp, label %loop1, label %loop2
37 %indvar.2 = phi i64 [ %indvar.2.next, %loop2 ], [ 1, %loop1 ]
/external/llvm-project/llvm/test/CodeGen/AArch64/
Dfalkor-hwpf.ll44 br label %loop1
46 loop1:
47 %iv1 = phi i32 [ 0, %entry ], [ %inc1, %loop1.latch ]
48 %outer.sum = phi i32 [ 0, %entry ], [ %sum, %loop1.latch ]
67 br label %loop1.latch
69 loop1.latch:
72 br i1 %exitcnd2, label %exit, label %loop1

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