| /external/arm-trusted-firmware/plat/mediatek/mt8173/include/ |
| D | mt8173_def.h | 118 #define mtk_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \ argument
119 (((lvl0_state) << PSTATE_ID_SHIFT) | ((type) << PSTATE_TYPE_SHIFT))
121 #define mtk_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \ argument
122 (((lvl0_state) << PSTATE_ID_SHIFT) | \
129 #define mtk_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type) \ argument
131 mtk_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type))
135 lvl2_state, lvl1_state, lvl0_state, pwr_lvl, type) \ argument
137 mtk_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type))
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| /external/arm-trusted-firmware/plat/qti/common/src/ |
| D | qti_pm.c | 28 #define qti_make_pwrstate_lvl0(lvl0_state, type) \ argument
29 (((lvl0_state) << PSTATE_ID_SHIFT) | ((type) << PSTATE_TYPE_SHIFT))
32 #define qti_make_pwrstate_lvl1(lvl1_state, lvl0_state, type) \ argument
34 qti_make_pwrstate_lvl0(lvl0_state, type))
37 #define qti_make_pwrstate_lvl2(lvl2_state, lvl1_state, lvl0_state, type) \ argument
39 qti_make_pwrstate_lvl1(lvl1_state, lvl0_state, type))
42 #define qti_make_pwrstate_lvl3(lvl3_state, lvl2_state, lvl1_state, lvl0_state, type) \ argument
44 qti_make_pwrstate_lvl2(lvl2_state, lvl1_state, lvl0_state, type))
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| /external/arm-trusted-firmware/plat/qemu/common/ |
| D | qemu_pm.c | 28 #define qemu_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \ argument
29 (((lvl0_state) << PSTATE_ID_SHIFT) | \
32 #define qemu_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \ argument
33 (((lvl0_state) << PSTATE_ID_SHIFT) | \
39 #define qemu_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type) \ argument
41 qemu_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type))
|
| /external/arm-trusted-firmware/plat/qemu/qemu_sbsa/ |
| D | sbsa_pm.c | 36 #define qemu_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \ argument
37 (((lvl0_state) << PSTATE_ID_SHIFT) | \
40 #define qemu_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \ argument
41 (((lvl0_state) << PSTATE_ID_SHIFT) | \
47 #define qemu_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type) \ argument
49 qemu_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type))
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| /external/arm-trusted-firmware/include/plat/arm/common/ |
| D | plat_arm.h | 121 #define arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \ argument
122 (((lvl0_state) << PSTATE_ID_SHIFT) | ((type) << PSTATE_TYPE_SHIFT))
124 #define arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \ argument
125 (((lvl0_state) << PSTATE_ID_SHIFT) | \
131 #define arm_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type) \ argument
133 arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type))
136 #define arm_make_pwrstate_lvl2(lvl2_state, lvl1_state, lvl0_state, pwr_lvl, type) \ argument
138 arm_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type))
|
| /external/arm-trusted-firmware/plat/rpi/common/ |
| D | rpi3_pm.c | 27 #define rpi3_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \ argument
28 (((lvl0_state) << PSTATE_ID_SHIFT) | \
33 #define rpi3_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \ argument
34 (((lvl0_state) << PSTATE_ID_SHIFT) | \
40 #define rpi3_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type) \ argument
42 rpi3_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type))
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| /external/arm-trusted-firmware/plat/mediatek/mt8183/ |
| D | plat_pm.c | 53 #define mtk_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \ argument
54 (((lvl0_state) << PSTATE_ID_SHIFT) | ((type) << PSTATE_TYPE_SHIFT))
58 #define mtk_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \ argument
59 (((lvl0_state) << PSTATE_ID_SHIFT) | \
66 #define mtk_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type) \ argument
68 mtk_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type))
72 lvl2_state, lvl1_state, lvl0_state, pwr_lvl, type) \ argument
74 mtk_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type))
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