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Searched refs:lwm16 (Results 1 – 25 of 25) sorted by relevance

/external/llvm/test/MC/Mips/
Dmicromips-loadstore-instructions.s35 # CHECK-EL: lwm16 $16, $17, $ra, 8($sp) # encoding: [0x12,0x45]
37 # CHECK-EL: lwm16 $16, $17, $ra, 8($sp) # encoding: [0x12,0x45]
81 # CHECK-EB: lwm16 $16, $17, $ra, 8($sp) # encoding: [0x45,0x12]
83 # CHECK-EB: lwm16 $16, $17, $ra, 8($sp) # encoding: [0x45,0x12]
124 lwm16 $16, $17, $ra, 8($sp)
Dmicromips-invalid.s22 lwm16 $5, $6, $ra, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: $16 or $31 expected
23 …lwm16 $16, $19, $ra, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: consecutive register numbers…
24 lwm16 $16-$25, $ra, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register operand
25 …lwm16 $16, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruct…
26 …lwm16 $16, $17, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruct…
27 …lwm16 $16-$20, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruct…
/external/llvm-project/llvm/test/MC/Mips/
Dmicromips-invalid.s22 lwm16 $5, $6, $ra, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: $16 or $31 expected
23 …lwm16 $16, $19, $ra, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: consecutive register numbers…
24 lwm16 $16-$25, $ra, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register operand
25 …lwm16 $16, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruct…
26 …lwm16 $16, $17, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruct…
27 …lwm16 $16-$20, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruct…
Dmicromips-loadstore-instructions.s44 # CHECK-EL: lwm16 $16, $17, $ra, 8($sp) # encoding: [0x12,0x45]
48 # CHECK-EL: lwm16 $16, $17, $ra, 8($sp) # encoding: [0x12,0x45]
103 # CHECK-EB: lwm16 $16, $17, $ra, 8($sp) # encoding: [0x45,0x12]
107 # CHECK-EB: lwm16 $16, $17, $ra, 8($sp) # encoding: [0x45,0x12]
150 lwm16 $16, $17, $ra, 8($sp)
/external/llvm/test/MC/Mips/micromips32r6/
Dinvalid.s86 lwm16 $5, $6, $ra, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: $16 or $31 expected
87 …lwm16 $16, $19, $ra, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: consecutive register numbers ex…
88 lwm16 $16-$25, $ra, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register operand
89 lwm16 $16, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
90 lwm16 $16, $17, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
91 lwm16 $16-$20, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
92 …lwm16 $16, $17, $ra, 8($fp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
93 …lwm16 $16, $17, $ra, 64($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
Dvalid.s72 lwm $16, $17, $ra, 8($sp) # CHECK: lwm16 $16, $17, $ra, 8($sp) # encoding: [0x45,0x22]
73 lwm16 $16, $17, $ra, 8($sp) # CHECK: lwm16 $16, $17, $ra, 8($sp) # encoding: [0x45,0x22]
/external/llvm/test/MC/Mips/micromips64r6/
Dinvalid.s113 lwm16 $5, $6, $ra, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: $16 or $31 expected
114 …lwm16 $16, $19, $ra, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: consecutive register numbers ex…
115 lwm16 $16-$25, $ra, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register operand
116 lwm16 $16, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
117 lwm16 $16, $17, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
118 lwm16 $16-$20, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
119 …lwm16 $16, $17, $ra, 8($fp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
120 …lwm16 $16, $17, $ra, 64($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
Dvalid.s151 lwm $16, $17, $ra, 8($sp) # CHECK: lwm16 $16, $17, $ra, 8($sp) # encoding: [0x45,0x22]
152 lwm16 $16, $17, $ra, 8($sp) # CHECK: lwm16 $16, $17, $ra, 8($sp) # encoding: [0x45,0x22]
/external/llvm-project/llvm/test/MC/Mips/micromips32r6/
Dinvalid.s89 lwm16 $5, $6, $ra, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: $16 or $31 expected
90 …lwm16 $16, $19, $ra, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: consecutive register numbers ex…
91 lwm16 $16-$25, $ra, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register operand
92 lwm16 $16, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
93 lwm16 $16, $17, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
94 lwm16 $16-$20, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
95 …lwm16 $16, $17, $ra, 8($fp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
96 …lwm16 $16, $17, $ra, 64($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
Dvalid.s90 lwm $16, $17, $ra, 8($sp) # CHECK: lwm16 $16, $17, $ra, 8($sp) # encoding: [0x45,0x22]
91 lwm16 $16, $17, $ra, 8($sp) # CHECK: lwm16 $16, $17, $ra, 8($sp) # encoding: [0x45,0x22]
/external/llvm-project/llvm/test/MC/Mips/micromips/
Dvalid.s82 lwm16 $16, $17, $ra, 8($sp) # CHECK: lwm16 $16, $17, $ra, 8($sp) # encoding: [0x45,0x12] label
/external/llvm/test/MC/Disassembler/Mips/micromips32r3/
Dvalid-el.txt47 0x12 0x45 # CHECK: lwm16 $16, $17, $ra, 8($sp)
Dvalid.txt47 0x45 0x12 # CHECK: lwm16 $16, $17, $ra, 8($sp)
/external/llvm-project/llvm/test/MC/Disassembler/Mips/micromips32r3/
Dvalid-el.txt48 0x12 0x45 # CHECK: lwm16 $16, $17, $ra, 8($sp)
Dvalid.txt48 0x45 0x12 # CHECK: lwm16 $16, $17, $ra, 8($sp)
/external/llvm/test/MC/Disassembler/Mips/micromips64r6/
Dvalid.txt160 0x45 0x22 # CHECK: lwm16 $16, $17, $ra, 8($sp)
/external/llvm-project/llvm/test/MC/Disassembler/Mips/micromips32r6/
Dvalid.txt256 0x45 0x22 # CHECK: lwm16 $16, $17, $ra, 8($sp)
/external/llvm/test/MC/Disassembler/Mips/micromips32r6/
Dvalid.txt252 0x45 0x22 # CHECK: lwm16 $16, $17, $ra, 8($sp)
/external/llvm/lib/Target/Mips/
DMicroMips32r6InstrInfo.td1173 !strconcat("lwm16", "\t$rt, $addr"), [],
1175 MMR6Arch<"lwm16">, MicroMipsR6Inst16 {
DMicroMipsInstrInfo.td662 def LWM16_MM : LoadMultMM16<"lwm16">, LWM_FM_MM16<0x4>,
/external/llvm-project/llvm/lib/Target/Mips/
DMicroMips32r6InstrInfo.td1182 !strconcat("lwm16", "\t$rt, $addr"), [],
1184 MMR6Arch<"lwm16"> {
DMicroMipsInstrInfo.td706 def LWM16_MM : LoadMultMM16<"lwm16", II_LWM>, LWM_FM_MM16<0x4>,
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMicroMips32r6InstrInfo.td1182 !strconcat("lwm16", "\t$rt, $addr"), [],
1184 MMR6Arch<"lwm16"> {
DMicroMipsInstrInfo.td706 def LWM16_MM : LoadMultMM16<"lwm16", II_LWM>, LWM_FM_MM16<0x4>,
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/
DMipsGenAsmMatcher.inc5033 "lw16\004lwc1\004lwc2\004lwc3\003lwe\003lwl\004lwle\003lwm\005lwm16\005l"
6909 …{ 5644 /* lwm16 */, Mips::LWM16_MM, Convert__RegList161_0__MemOffsetUimm42_1, AMFBS_InMicroMips_No…
6910 …{ 5644 /* lwm16 */, Mips::LWM16_MMR6, Convert__RegList161_0__MemOffsetUimm42_1, AMFBS_InMicroMips_…
10248 { 5644 /* lwm16 */, 2 /* 1 */, MCK_MemOffsetUimm4, AMFBS_InMicroMips_NotMips32r6 },
10249 { 5644 /* lwm16 */, 1 /* 0 */, MCK_RegList16, AMFBS_InMicroMips_NotMips32r6 },
10250 { 5644 /* lwm16 */, 2 /* 1 */, MCK_MemOffsetUimm4, AMFBS_InMicroMips_HasMips32r6 },
10251 { 5644 /* lwm16 */, 1 /* 0 */, MCK_RegList16, AMFBS_InMicroMips_HasMips32r6 },