Searched refs:m_cfg (Results 1 – 10 of 10) sorted by relevance
69 operator const ocsd_etmv4_cfg &() const { return m_cfg; };71 operator const ocsd_etmv4_cfg *() const { return &m_cfg; };73 const ocsd_core_profile_t &coreProfile() const { return m_cfg.core_prof; }; in coreProfile()74 const ocsd_arch_version_t &archVersion() const { return m_cfg.arch_ver; }; in archVersion()188 ocsd_etmv4_cfg m_cfg;197 return (bool)((m_cfg.reg_idr0 & 0x6) == 0x6); in LSasInstP0()202 return (bool)((m_cfg.reg_idr0 & 0x18) == 0x18); in hasDataTrace()207 return (bool)((m_cfg.reg_idr0 & 0x20) == 0x20); in hasBranchBroadcast()212 return (bool)((m_cfg.reg_idr0 & 0x40) == 0x40); in hasCondTrace()217 return (bool)((m_cfg.reg_idr0 & 0x80) == 0x80); in hasCycleCountI()[all …]
71 operator const ocsd_stm_cfg &() const { return m_cfg; };73 operator const ocsd_stm_cfg *() const { return &m_cfg; };87 ocsd_stm_cfg m_cfg; variable92 m_cfg.reg_tcsr = 0; in STMConfig()93 m_cfg.reg_devid = 0xFF; // default to 256 masters. in STMConfig()94 m_cfg.reg_feat3r = 0x10000; // default to 65536 channels. in STMConfig()95 m_cfg.reg_feat1r = 0x0; in STMConfig()96 m_cfg.reg_hwev_mast = 0; // default hwtrace master = 0; in STMConfig()97 m_cfg.hw_event = HwEvent_Unknown_Disabled; // default to not present / disabled. in STMConfig()103 m_cfg = *cfg_regs; in STMConfig()[all …]
39 m_cfg.reg_idr0 = 0x28000EA1; in EtmV4Config()40 m_cfg.reg_idr1 = 0x4100F403; in EtmV4Config()41 m_cfg.reg_idr2 = 0x00000488; in EtmV4Config()42 m_cfg.reg_idr8 = 0; in EtmV4Config()43 m_cfg.reg_idr9 = 0; in EtmV4Config()44 m_cfg.reg_idr10 = 0; in EtmV4Config()45 m_cfg.reg_idr11 = 0; in EtmV4Config()46 m_cfg.reg_idr12 = 0; in EtmV4Config()47 m_cfg.reg_idr13 = 0; in EtmV4Config()48 m_cfg.reg_configr = 0xC1; in EtmV4Config()[all …]
85 operator const ocsd_etmv3_cfg &() const { return m_cfg; };87 operator const ocsd_etmv3_cfg *() const { return &m_cfg; };128 ocsd_etmv3_cfg m_cfg;137 m_cfg = *p_cfg;143 return (bool)((m_cfg.reg_ctrl & CTRL_CYCLEACC) != 0); in isCycleAcc()149 return ((int)m_cfg.reg_idr & 0xF0) >> 4; in MinorRev()154 return (bool)((m_cfg.reg_ctrl & CTRL_DATAONLY) == 0); in isInstrTrace()159 return (bool)((m_cfg.reg_ctrl & CTRL_DATAVAL) != 0); in isDataValTrace()164 return (bool)((m_cfg.reg_ctrl & CTRL_DATAADDR) != 0); in isDataAddrTrace()170 return (bool)((m_cfg.reg_ctrl & (CTRL_DATAADDR | CTRL_DATAVAL)) != 0); in isDataTrace()[all …]
90 operator const ocsd_ptm_cfg &() const { return m_cfg; };92 operator const ocsd_ptm_cfg *() const { return &m_cfg; };118 const ocsd_core_profile_t &coreProfile() const { return m_cfg.core_prof; }; in coreProfile()119 const ocsd_arch_version_t &archVersion() const { return m_cfg.arch_ver; }; in archVersion()122 ocsd_ptm_cfg m_cfg;130 m_cfg = *p_cfg;136 return (bool)((m_cfg.reg_ctrl & CTRL_BRANCH_BCAST) != 0); in enaBranchBCast()141 return (bool)((m_cfg.reg_ctrl & CTRL_CYCLEACC) != 0); in enaCycleAcc()146 return (bool)((m_cfg.reg_ctrl & CTRL_RETSTACK_ENA) != 0); in enaRetStack()151 return (bool)((m_cfg.reg_ccer & CCER_RESTACK_IMPL) != 0); in hasRetStack()[all …]
79 m_cfg.reg_idr0 = m_ete_cfg.reg_idr0; in copyV4()80 m_cfg.reg_idr1 = m_ete_cfg.reg_idr1; in copyV4()81 m_cfg.reg_idr2 = m_ete_cfg.reg_idr2; in copyV4()82 m_cfg.reg_idr8 = m_ete_cfg.reg_idr8; in copyV4()83 m_cfg.reg_idr9 = 0; in copyV4()84 m_cfg.reg_idr10 = 0; in copyV4()85 m_cfg.reg_idr11 = 0; in copyV4()86 m_cfg.reg_idr12 = 0; in copyV4()87 m_cfg.reg_idr13 = 0; in copyV4()88 m_cfg.reg_configr = m_ete_cfg.reg_configr; in copyV4()[all …]
43 m_cfg.object.egl = &egl; in CandidateConfig()44 m_cfg.object.display = display; in CandidateConfig()45 m_cfg.object.config = config; in CandidateConfig()51 m_cfg.configInfo = &configInfo; in CandidateConfig()57 return m_cfg.configInfo->getAttribute(attrib); in get()62 …const std::vector<std::string> extensions = getDisplayExtensions(*m_cfg.object.egl, m_cfg.object.d… in get()65 return getConfigAttribInt(*m_cfg.object.egl, m_cfg.object.display, m_cfg.object.config, attrib); in get()70 return getConfigAttribInt(*m_cfg.object.egl, m_cfg.object.display, m_cfg.object.config, attrib); in get()
85 } m_cfg; member in eglu::CandidateConfig
40 m_cfg.arch_ver = ARCH_V7; in PtmConfig()41 m_cfg.core_prof = profile_CortexA; in PtmConfig()42 m_cfg.reg_ccer = 0; in PtmConfig()43 m_cfg.reg_idr = 0x4100F310; in PtmConfig()44 m_cfg.reg_ctrl = 0; in PtmConfig()49 m_cfg = *cfg_regs; in PtmConfig()55 return ctxtIdsizes[(m_cfg.reg_ctrl >> 14) & 0x3]; in CtxtIDBytes()
41 m_cfg.arch_ver = ARCH_V7; in EtmV3Config()42 m_cfg.core_prof = profile_CortexA; in EtmV3Config()43 m_cfg.reg_ccer = 0; in EtmV3Config()44 m_cfg.reg_idr = 0x4100F240; // default trace IDR value in EtmV3Config()45 m_cfg.reg_ctrl = 0; in EtmV3Config()50 m_cfg = *cfg_regs; in EtmV3Config()62 return ctxtIdsizes[(m_cfg.reg_ctrl >> 14) & 0x3]; in CtxtIDBytes()