| /external/llvm-project/llvm/test/CodeGen/AArch64/ |
| D | mul-lohi.ll | 7 ; CHECK: madd [[TEMP1:x[0-9]+]], x0, x3, [[HI]]
8 ; CHECK-DAG: madd x1, x1, x2, [[TEMP1]]
14 ; CHECK-BE: madd [[TEMP1:x[0-9]+]], x1, x2, [[HI]]
15 ; CHECK-BE-DAG: madd x0, x0, x3, [[TEMP1]]
23 ; The machine combiner should create madd instructions when
29 ; CHECK-NEXT: madd [[TEMP1:x[0-9]+]], x0, x3, [[HI]]
30 ; CHECK-DAG: madd x1, x1, x2, [[TEMP1]]
41 ; CHECK-NEXT: madd [[TEMP1:x[0-9]+]], x0, x3, [[HI]]
42 ; CHECK-DAG: madd x1, x1, x2, [[TEMP1]]
|
| D | madd-lohi.ll | 7 ; CHECK-DAG: madd [[PART1:x[0-9]+]], x0, x3, [[CARRY]]
8 ; CHECK: madd x1, x1, x2, [[PART1]]
13 ; CHECK-BE-DAG: madd [[PART1:x[0-9]+]], x1, x2, [[CARRY]]
14 ; CHECK-BE: madd x0, x0, x3, [[PART1]]
|
| D | urem-seteq-nonzero.ll | 10 ; CHECK-NEXT: madd w8, w0, w8, w9
25 ; CHECK-NEXT: madd w8, w0, w8, w9
42 ; CHECK-NEXT: madd w8, w0, w8, w9
57 ; CHECK-NEXT: madd w8, w0, w8, w9
73 ; CHECK-NEXT: madd w8, w0, w8, w9
89 ; CHECK-NEXT: madd w8, w0, w8, w9
106 ; CHECK-NEXT: madd w8, w0, w8, w9
124 ; CHECK-NEXT: madd w8, w0, w8, w9
161 ; CHECK-NEXT: madd w8, w0, w8, w9
180 ; CHECK-NEXT: madd w8, w0, w8, w9
[all …]
|
| D | srem-seteq.ll | 15 ; CHECK-NEXT: madd w8, w0, w8, w9
33 ; CHECK-NEXT: madd w8, w0, w8, w9
52 ; CHECK-NEXT: madd w8, w0, w8, w9
69 ; CHECK-NEXT: madd w8, w0, w8, w9
112 ; CHECK-NEXT: madd w8, w0, w8, w9
132 ; CHECK-NEXT: madd w8, w0, w8, w9
150 ; CHECK-NEXT: madd w8, w0, w8, w9
173 ; CHECK-NEXT: madd w8, w0, w8, w9
193 ; CHECK-NEXT: madd w8, w0, w8, w9
211 ; CHECK-NEXT: madd w8, w0, w8, w9
|
| D | midpoint-int.ll | 23 ; CHECK-NEXT: madd w0, w9, w8, w0
46 ; CHECK-NEXT: madd w0, w9, w8, w0
72 ; CHECK-NEXT: madd w0, w10, w9, w8
97 ; CHECK-NEXT: madd w0, w8, w9, w0
123 ; CHECK-NEXT: madd w0, w9, w10, w8
154 ; CHECK-NEXT: madd x0, x9, x8, x0
177 ; CHECK-NEXT: madd x0, x9, x8, x0
203 ; CHECK-NEXT: madd x0, x10, x9, x8
228 ; CHECK-NEXT: madd x0, x8, x9, x0
254 ; CHECK-NEXT: madd x0, x9, x10, x8
[all …]
|
| D | aarch64-fix-cortex-a53-835769.ll | 33 ; CHECK-NEXT: madd
36 ; CHECK-NOWORKAROUND-NEXT: madd
39 ; CHECK-BASIC-PASS-DISABLED-NEXT: madd
51 ; CHECK-NEXT: madd
54 ; CHECK-NOWORKAROUND-NEXT: madd
312 ; CHECK-NEXT: madd
315 ; CHECK-NOWORKAROUND-NEXT: madd
328 ; CHECK-NEXT: madd
331 ; CHECK-NOWORKAROUND-NEXT: madd
409 ; CHECK-NEXT: madd
[all …]
|
| D | fast-isel-gep.ll | 15 ; CHECK-NEXT: madd x0, x1, [[REG]], x0
46 ; CHECK-NEXT: madd {{x[0-9]+}}, [[REG1]], [[REG2]], x0
|
| /external/llvm/test/CodeGen/AArch64/ |
| D | madd-lohi.ll | 7 ; CHECK-DAG: madd [[PART1:x[0-9]+]], x0, x3, [[CARRY]]
8 ; CHECK: madd x1, x1, x2, [[PART1]]
13 ; CHECK-BE-DAG: madd [[PART1:x[0-9]+]], x1, x2, [[CARRY]]
14 ; CHECK-BE: madd x0, x0, x3, [[PART1]]
|
| D | mul-lohi.ll | 21 ; The machine combiner should create madd instructions when
27 ; CHECK-NEXT: madd [[TEMP1:x[0-9]+]], x0, x3, [[HI]]
28 ; CHECK-NEXT: madd x1, x1, x2, [[TEMP1]]
39 ; CHECK-NEXT: madd [[TEMP1:x[0-9]+]], x0, x3, [[HI]]
40 ; CHECK-NEXT: madd x1, x1, x2, [[TEMP1]]
|
| D | aarch64-fix-cortex-a53-835769.ll | 33 ; CHECK-NEXT: madd
36 ; CHECK-NOWORKAROUND-NEXT: madd
39 ; CHECK-BASIC-PASS-DISABLED-NEXT: madd
51 ; CHECK-NEXT: madd
54 ; CHECK-NOWORKAROUND-NEXT: madd
312 ; CHECK-NEXT: madd
315 ; CHECK-NOWORKAROUND-NEXT: madd
328 ; CHECK-NEXT: madd
331 ; CHECK-NOWORKAROUND-NEXT: madd
409 ; CHECK-NEXT: madd
[all …]
|
| /external/arm-trusted-firmware/plat/arm/board/morello/aarch64/ |
| D | morello_helper.S | 49 madd x2, x3, x4, x2
51 madd x1, x2, x4, x1
53 madd x0, x1, x4, x0
|
| /external/arm-trusted-firmware/plat/arm/board/n1sdp/aarch64/ |
| D | n1sdp_helper.S | 48 madd x2, x3, x4, x2
50 madd x1, x2, x4, x1
52 madd x0, x1, x4, x0
|
| /external/arm-trusted-firmware/plat/arm/css/sgi/aarch64/ |
| D | sgi_helper.S | 51 madd x2, x3, x4, x2
53 madd x1, x2, x4, x1
55 madd x0, x1, x4, x0
|
| /external/llvm/test/MC/Mips/ |
| D | micromips-multiply-instructions.s | 12 # CHECK-EL: madd $4, $5 # encoding: [0xa4,0x00,0x3c,0xcb]
19 # CHECK-EB: madd $4, $5 # encoding: [0x00,0xa4,0xcb,0x3c]
23 madd $4, $5
|
| /external/llvm-project/llvm/test/MC/Mips/ |
| D | micromips-multiply-instructions.s | 12 # CHECK-EL: madd $4, $5 # encoding: [0xa4,0x00,0x3c,0xcb]
19 # CHECK-EB: madd $4, $5 # encoding: [0x00,0xa4,0xcb,0x3c]
23 madd $4, $5
|
| /external/llvm-project/llvm/test/CodeGen/Mips/ |
| D | inlineasm-constraint-reg.ll | 37 ; CHECK-NEXT: madd ${{[0-9]+}}, ${{[0-9]+}}
41 …call i32 asm sideeffect "\09mtlo $3 \0A\09\09madd $1, $2 ", "=l,r,r,r"(i32 7, i32 6, i32 44) nounw…
47 ; CHECK-NEXT: madd ${{[0-9]+}}, ${{[0-9]+}}
51 …call i16 asm sideeffect "\09mtlo $3 \0A\09\09madd $1, $2 ", "=l,r,r,r"(i32 7, i32 6, i32 44) nounw…
|
| D | fmadd1.ll | 1 ; Check that madd.[ds], msub.[ds], nmadd.[ds], and nmsub.[ds] are supported
21 ; Check that madd.[ds], msub.[ds], nmadd.[ds], and nmsub.[ds] are not generated
43 ; 32R2: madd.s $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
53 ; 64-DAG: madd.s $[[T0:f[0-9]+]], $f14, $f12, $f13
57 ; 64R2: madd.s $[[T0:f[0-9]+]], $f14, $f12, $f13
126 ; 32R2-NAN: madd.s $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
138 ; 64-NAN: madd.s $[[T0:f[0-9]+]], $f14, $f12, $f13
144 ; 64R2-NAN: madd.s $[[T0:f[0-9]+]], $f14, $f12, $f13
209 ; 32R2: madd.d $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
220 ; 64-DAG: madd.d $[[T0:f[0-9]+]], $f14, $f12, $f13
[all …]
|
| /external/eigen/Eigen/src/Core/products/ |
| D | GeneralBlockPanelKernel.h | 435 …EIGEN_STRONG_INLINE void madd(const LhsPacketType& a, const RhsPacketType& b, AccPacketType& c, Ac…
537 …EIGEN_STRONG_INLINE void madd(const LhsPacket& a, const RhsPacket& b, AccPacket& c, RhsPacket& tmp…
701 …EIGEN_STRONG_INLINE void madd(const LhsPacket& a, const RhsPacket& b, DoublePacketType& c, RhsPack…
707 …EIGEN_STRONG_INLINE void madd(const LhsPacket& a, const RhsPacket& b, ResPacket& c, RhsPacket& /*t…
821 …EIGEN_STRONG_INLINE void madd(const LhsPacket& a, const RhsPacket& b, AccPacket& c, RhsPacket& tmp…
980 traits.madd(A0, B_0, C0, T0); \
981 traits.madd(A1, B_0, C4, T0); \
982 traits.madd(A2, B_0, C8, B_0); \
984 traits.madd(A0, B_0, C1, T0); \
985 traits.madd(A1, B_0, C5, T0); \
[all …]
|
| /external/arm-trusted-firmware/plat/arm/board/tc0/include/ |
| D | tc0_helpers.S | 46 madd x1, x2, x4, x1
48 madd x0, x1, x5, x0
|
| /external/llvm/test/CodeGen/Mips/ |
| D | fmadd1.ll | 1 ; Check that madd.[ds], msub.[ds], nmadd.[ds], and nmsub.[ds] are supported
32 ; 32R2: madd.s $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
42 ; 64-DAG: madd.s $[[T0:f[0-9]+]], $f14, $f12, $f13
46 ; 64R2: madd.s $[[T0:f[0-9]+]], $f14, $f12, $f13
115 ; 32R2-NAN: madd.s $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
127 ; 64-NAN: madd.s $[[T0:f[0-9]+]], $f14, $f12, $f13
133 ; 64R2-NAN: madd.s $[[T0:f[0-9]+]], $f14, $f12, $f13
198 ; 32R2: madd.d $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
209 ; 64-DAG: madd.d $[[T0:f[0-9]+]], $f14, $f12, $f13
213 ; 64R2: madd.d $[[T0:f[0-9]+]], $f14, $f12, $f13
[all …]
|
| /external/arm-trusted-firmware/plat/arm/css/sgm/aarch64/ |
| D | css_sgm_helpers.S | 48 madd x1, x2, x4, x1
50 madd x0, x1, x5, x0
|
| /external/llvm-project/llvm/test/CodeGen/PowerPC/ |
| D | vmladduhm.ll | 15 define <8 x i16> @madd(<8 x i16> %m, <8 x i16> %n, <8 x i16> %o) {
16 ; CHECK-LABEL: madd:
|
| /external/arm-trusted-firmware/plat/arm/board/fvp/aarch64/ |
| D | fvp_helpers.S | 173 madd x1, x2, x4, x1
175 madd x0, x1, x5, x0
|
| /external/capstone/suite/MC/Mips/ |
| D | mips-dsp-instructions.s.cs | 26 0x70,0xc7,0x08,0x00 = madd $ac1, $a2, $a3
36 0x70,0xc7,0x00,0x00 = madd $a2, $a3
|
| /external/llvm/test/MC/Mips/mips32r6/ |
| D | invalid-mips32r2.s | 8 …madd.d $f18,$f19,$f26,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
9 …madd.s $f1,$f31,$f19,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
|