| /external/llvm-project/llvm/test/CodeGen/Mips/Fast-ISel/ |
| D | simplestorefp1.ll | 3 ; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \
7 ; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \
8 ; RUN: < %s | FileCheck %s -check-prefix=mips32
41 ; mips32: .ent d1
42 ; mips32: lui $[[REG1a:[0-9]+]], 16371
43 ; mips32: ori $[[REG2a:[0-9]+]], $[[REG1a]], 49353
44 ; mips32: lui $[[REG1b:[0-9]+]], 21403
45 ; mips32: ori $[[REG2b:[0-9]+]], $[[REG1b]], 34951
46 ; mips32: mtc1 $[[REG2b]], $f[[REG3:[0-9]+]]
47 ; mips32: mtc1 $[[REG2a]], $f{{[0-9]+}}
[all …]
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| D | loadstoreconv.ll | 3 ; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \
7 ; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \
8 ; RUN: < %s | FileCheck %s -check-prefix=mips32
72 ; mips32-LABEL: .ent _Z4sc_iv
82 ; mips32: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}})
83 ; mips32: sll $[[REG2:[0-9]+]], $[[REG1]], 24
84 ; mips32: sra ${{[0-9]+}}, $[[REG2]], 24
110 ; mips32=LABEL: .ent _Z4ss_iv
120 ; mips32: lhu $[[REG1:[0-9]+]], 0(${{[0-9]+}})
121 ; mips32: sll $[[REG2:[0-9]+]], $[[REG1]], 16
[all …]
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| /external/llvm/test/CodeGen/Mips/Fast-ISel/ |
| D | simplestorefp1.ll | 3 ; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 \
7 ; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 \
8 ; RUN: < %s | FileCheck %s -check-prefix=mips32
41 ; mips32: .ent d1
42 ; mips32: lui $[[REG1a:[0-9]+]], 16371
43 ; mips32: ori $[[REG2a:[0-9]+]], $[[REG1a]], 49353
44 ; mips32: lui $[[REG1b:[0-9]+]], 21403
45 ; mips32: ori $[[REG2b:[0-9]+]], $[[REG1b]], 34951
46 ; mips32: mtc1 $[[REG2b]], $f[[REG3:[0-9]+]]
47 ; mips32: mtc1 $[[REG2a]], $f{{[0-9]+}}
[all …]
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| D | loadstoreconv.ll | 3 ; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 \
7 ; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 \
8 ; RUN: < %s | FileCheck %s -check-prefix=mips32
72 ; mips32-LABEL: .ent _Z4sc_iv
82 ; mips32: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}})
83 ; mips32: sll $[[REG2:[0-9]+]], $[[REG1]], 24
84 ; mips32: sra ${{[0-9]+}}, $[[REG2]], 24
110 ; mips32=LABEL: .ent _Z4ss_iv
120 ; mips32: lhu $[[REG1:[0-9]+]], 0(${{[0-9]+}})
121 ; mips32: sll $[[REG2:[0-9]+]], $[[REG1]], 16
[all …]
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| /external/llvm/test/MC/Mips/ |
| D | set-mips-directives.s | 16 .set mips32 define
20 .set mips32 define
23 .set mips32 define
52 # CHECK: .set mips32
56 # CHECK: .set mips32
59 # CHECK: .set mips32
|
| D | set-arch.s | 1 # RUN: llvm-mc %s -triple=mipsel-unknown-linux -show-encoding -mcpu=mips32 | \
15 .set arch=mips32
19 .set arch=mips32
22 .set arch=mips32
54 # CHECK: .set arch=mips32
|
| D | directive-ent.s | 4 # RUN: llvm-mc -mcpu=mips32 -triple mips-unknown-unknown %s | \
6 # RUN: llvm-mc -filetype=obj -mcpu=mips32 -triple mips-unknown-unknown %s | \
10 # RUN: llvm-mc -mcpu=mips32 -mattr=micromips -triple mips-unknown-unknown %s | \
12 # RUN: llvm-mc -filetype=obj -mcpu=mips32 -mattr=micromips \
|
| D | llvm-mc-fixup-endianness.s | 1 # RUN: llvm-mc -show-encoding -mcpu=mips32 -triple mips-unknown-unknown %s | FileCheck -check-prefi…
2 # RUN: llvm-mc -show-encoding -mcpu=mips32 -triple mipsel-unknown-unknown %s | FileCheck -check-pre…
|
| D | elf_eflags_nan2008.s | 1 # RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips32 %s -o - | \
4 # RUN: llvm-mc -triple mipsel-unknown-linux -mcpu=mips32 %s -o -| \
|
| D | elf_eflags_nanlegacy.s | 1 # RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips32 %s -o - | \
4 # RUN: llvm-mc -triple mipsel-unknown-linux -mcpu=mips32 %s -o -| \
|
| D | elf_eflags_micromips.s | 1 # RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips32 \
4 # RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips32 %s -o - \
|
| D | module-softfloat.s | 1 # RUN: llvm-mc %s -arch=mips -mcpu=mips32 | \
4 # RUN: llvm-mc %s -arch=mips -mcpu=mips32 -filetype=obj -o - | \
|
| /external/llvm-project/llvm/test/MC/Mips/ |
| D | set-mips-directives.s | 16 .set mips32 define
20 .set mips32 define
23 .set mips32 define
52 # CHECK: .set mips32
56 # CHECK: .set mips32
59 # CHECK: .set mips32
|
| D | set-arch.s | 1 # RUN: llvm-mc %s -triple=mipsel-unknown-linux -show-encoding -mcpu=mips32 | \
15 .set arch=mips32
19 .set arch=mips32
22 .set arch=mips32
56 # CHECK: .set arch=mips32
|
| D | directive-ent.s | 4 # RUN: llvm-mc -mcpu=mips32 -triple mips-unknown-unknown %s | \
6 # RUN: llvm-mc -filetype=obj -mcpu=mips32 -triple mips-unknown-unknown %s | \
10 # RUN: llvm-mc -mcpu=mips32 -mattr=micromips -triple mips-unknown-unknown %s | \
12 # RUN: llvm-mc -filetype=obj -mcpu=mips32 -mattr=micromips \
|
| D | llvm-mc-fixup-endianness.s | 1 # RUN: llvm-mc -show-encoding -mcpu=mips32 -triple mips-unknown-unknown %s | FileCheck -check-prefi…
2 # RUN: llvm-mc -show-encoding -mcpu=mips32 -triple mipsel-unknown-unknown %s | FileCheck -check-pre…
|
| D | elf_eflags_nan2008.s | 1 # RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips32 %s -o - | \
4 # RUN: llvm-mc -triple mipsel-unknown-linux -mcpu=mips32 %s -o -| \
|
| D | elf_eflags_nanlegacy.s | 1 # RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips32 %s -o - | \
4 # RUN: llvm-mc -triple mipsel-unknown-linux -mcpu=mips32 %s -o -| \
|
| D | elf_eflags_micromips.s | 1 # RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips32 \
4 # RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips32 %s -o - \
|
| D | module-softfloat.s | 1 # RUN: llvm-mc %s -arch=mips -mcpu=mips32 | \
4 # RUN: llvm-mc %s -arch=mips -mcpu=mips32 -filetype=obj -o - | \
|
| /external/llvm-project/llvm/test/CodeGen/Mips/ |
| D | fabs.ll | 11 ; RUN: llc < %s -mtriple=mipsel-linux-gnu -mcpu=mips32 | FileCheck %s \
23 ; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32 | FileCheck %s \
45 ; RUN: llc < %s -mtriple=mipsel-linux-gnu -mcpu=mips32 \
49 ; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32 \
56 ; RUN: llc < %s -mtriple=mipsel-linux-gnu -mcpu=mips32 -mattr=+micromips \
60 ; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32 -mattr=+micromips \
70 ; RUN: llc < %s -mtriple=mipsel-linux-gnu -mcpu=mips32 -mattr=+micromips \
72 ; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32 -mattr=+micromips \
|
| D | abicalls.ll | 1 ; RUN: llc -filetype=asm -mtriple mipsel-unknown-linux -mcpu=mips32 -relocation-model=static %s -o …
2 ; RUN: llc -filetype=asm -mtriple mipsel-unknown-linux -mcpu=mips32 -relocation-model=pic %s -o - |…
11 ; RUN: llc -filetype=asm -mtriple mipsel-unknown-linux -mcpu=mips32 -mattr noabicalls -relocation-m…
|
| /external/llvm/test/CodeGen/Mips/ |
| D | abicalls.ll | 1 ; RUN: llc -filetype=asm -mtriple mipsel-unknown-linux -mcpu=mips32 -relocation-model=static %s -o …
2 ; RUN: llc -filetype=asm -mtriple mipsel-unknown-linux -mcpu=mips32 -relocation-model=pic %s -o - |…
6 ; RUN: llc -filetype=asm -mtriple mipsel-unknown-linux -mcpu=mips32 -mattr noabicalls -relocation-m…
|
| /external/llvm-project/llvm/test/CodeGen/Mips/indirect-jump-hazard/ |
| D | unsupported-mips32.ll | 1 ; RUN: not --crash llc -mtriple=mips-unknown-linux -mcpu=mips32 -mattr=+use-indirect-jump-hazard %s…
3 ; Test that mips32 and indirect jump with hazard barriers is not supported.
|
| /external/llvm-project/lldb/source/Plugins/Process/Linux/ |
| D | NativeRegisterContextLinux_mips64.cpp | 56 struct mips32_watch_regs mips32; member
573 return regs->mips32.watchhi[index]; in GetWatchHi()
584 regs->mips32.watchhi[index] = value; in SetWatchHi()
594 return regs->mips32.watchlo[index]; in GetWatchLo()
605 regs->mips32.watchlo[index] = (uint32_t)value; in SetWatchLo()
615 return regs->mips32.watch_masks[index] & IRW; in GetIRWMask()
625 return regs->mips32.watch_masks[index] & ~IRW; in GetRegMask()
791 regs.mips32.watchlo[wp_index] = default_watch_regs.mips32.watchlo[wp_index]; in ClearHardwareWatchpoint()
792 regs.mips32.watchhi[wp_index] = default_watch_regs.mips32.watchhi[wp_index]; in ClearHardwareWatchpoint()
793 regs.mips32.watch_masks[wp_index] = in ClearHardwareWatchpoint()
[all …]
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