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Searched refs:mmio_write_32 (Results 1 – 25 of 365) sorted by relevance

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/external/arm-trusted-firmware/drivers/renesas/rcar/ddr/ddr_a/
Dddr_init_e3.c64 mmio_write_32(CPG_CPGWPR, 0x5A5AFFFF); in init_ddr()
65 mmio_write_32(CPG_CPGWPCR, 0xA5A50000); in init_ddr()
67 mmio_write_32(CPG_SRCR4, 0x20000000); in init_ddr()
69 mmio_write_32(0xE61500DC, 0xe2200000); /* Change to 1584Mbps */ in init_ddr()
73 mmio_write_32(CPG_SRSTCLR4, 0x20000000); in init_ddr()
75 mmio_write_32(CPG_CPGWPCR, 0xA5A50001); in init_ddr()
78 mmio_write_32(DBSC_DBSYSCNT0, 0x00001234); in init_ddr()
79 mmio_write_32(DBSC_DBKIND, 0x00000007); in init_ddr()
82 mmio_write_32(DBSC_DBMEMCONF_0_0, 0x0f030a02); /* 1GB */ in init_ddr()
84 mmio_write_32(DBSC_DBMEMCONF_0_0, 0x10030a02); /* 2GB(default) */ in init_ddr()
[all …]
Dddr_init_d3.c24 mmio_write_32(DBSC_DBSYSCNT0, 0x00001234); in init_ddr_d3_1866()
25 mmio_write_32(DBSC_DBKIND, 0x00000007); in init_ddr_d3_1866()
26 mmio_write_32(DBSC_DBMEMCONF_0_0, 0x0f030a01); in init_ddr_d3_1866()
27 mmio_write_32(DBSC_DBPHYCONF0, 0x00000001); in init_ddr_d3_1866()
28 mmio_write_32(DBSC_DBTR0, 0x0000000D); in init_ddr_d3_1866()
29 mmio_write_32(DBSC_DBTR1, 0x00000009); in init_ddr_d3_1866()
30 mmio_write_32(DBSC_DBTR2, 0x00000000); in init_ddr_d3_1866()
31 mmio_write_32(DBSC_DBTR3, 0x0000000D); in init_ddr_d3_1866()
32 mmio_write_32(DBSC_DBTR4, 0x000D000D); in init_ddr_d3_1866()
33 mmio_write_32(DBSC_DBTR5, 0x0000002D); in init_ddr_d3_1866()
[all …]
Dddr_init_v3m.c19 mmio_write_32(DBSC_DBSYSCNT0, 0x00001234); in init_ddr_v3m_1600()
20 mmio_write_32(DBSC_DBKIND, 0x00000007); in init_ddr_v3m_1600()
22 mmio_write_32(DBSC_DBMEMCONF_0_0, 0x0f030a02); // 1GB: Eagle in init_ddr_v3m_1600()
24 mmio_write_32(DBSC_DBMEMCONF_0_0, 0x10030a02); // 2GB: V3MSK in init_ddr_v3m_1600()
26 mmio_write_32(DBSC_DBPHYCONF0, 0x00000001); in init_ddr_v3m_1600()
27 mmio_write_32(DBSC_DBTR0, 0x0000000B); in init_ddr_v3m_1600()
28 mmio_write_32(DBSC_DBTR1, 0x00000008); in init_ddr_v3m_1600()
29 mmio_write_32(DBSC_DBTR3, 0x0000000B); in init_ddr_v3m_1600()
30 mmio_write_32(DBSC_DBTR4, 0x000B000B); in init_ddr_v3m_1600()
31 mmio_write_32(DBSC_DBTR5, 0x00000027); in init_ddr_v3m_1600()
[all …]
/external/arm-trusted-firmware/plat/hisilicon/hikey/
Dhikey_ddr.c26 mmio_write_32((0xf7032000 + 0x000), data); in init_pll()
34 mmio_write_32((0xf7800000 + 0x000), data); in init_pll()
40 mmio_write_32(PERI_SC_PERIPH_CTRL14, 0x2101); in init_pll()
44 mmio_write_32(PERI_SC_PERIPH_CTRL14, 0x2001); in init_pll()
48 mmio_write_32(PERI_SC_PERIPH_CTRL14, 0x2201); in init_pll()
52 mmio_write_32(0xf7032000 + 0x02c, 0x5110103e); in init_pll()
58 mmio_write_32(0xf7032000 + 0x050, data); in init_pll()
62 mmio_write_32(PERI_SC_PERIPH_CTRL14, 0x2101); in init_pll()
66 mmio_write_32(PERI_SC_PERIPH_CTRL14, 0x2001); in init_pll()
70 mmio_write_32(PERI_SC_PERIPH_CTRL14, 0x2201); in init_pll()
[all …]
Dhikey_bl2_setup.c190 mmio_write_32(PERI_SC_PERIPH_CLKDIS0, PERI_CLK0_MMC0); in reset_dwmmc_clk()
195 mmio_write_32(PERI_SC_PERIPH_CLKEN0, PERI_CLK0_MMC0); in reset_dwmmc_clk()
200 mmio_write_32(PERI_SC_PERIPH_RSTEN0, PERI_RST0_MMC0); in reset_dwmmc_clk()
205 mmio_write_32(PERI_SC_PERIPH_CTRL2, data); in reset_dwmmc_clk()
210 mmio_write_32(PERI_SC_PERIPH_CTRL13, data); in reset_dwmmc_clk()
216 mmio_write_32(PERI_SC_PERIPH_RSTDIS0, PERI_RST0_MMC0); in reset_dwmmc_clk()
227 mmio_write_32(MEMORY_AXI_CHIP_ADDR, midr); in hikey_boardid_init()
231 mmio_write_32(MEMORY_AXI_BOARD_TYPE_ADDR, 0); in hikey_boardid_init()
232 mmio_write_32(MEMORY_AXI_BOARD_ID_ADDR, 0x2b); in hikey_boardid_init()
234 mmio_write_32(ACPU_ARM64_FLAGA, 0x1234); in hikey_boardid_init()
[all …]
/external/arm-trusted-firmware/plat/hisilicon/hikey960/
Dhikey960_bl_common.c18 mmio_write_32(0xfff350b4, 0xf0002000); in hikey960_clk_init()
20 mmio_write_32(0xfff350bc, 0xfc004c00); in hikey960_clk_init()
32 mmio_write_32(PMC_PPLL3_CTRL0_REG, 0x4904305); in hikey960_enable_ppll3()
33 mmio_write_32(PMC_PPLL3_CTRL1_REG, 0x2300000); in hikey960_enable_ppll3()
34 mmio_write_32(PMC_PPLL3_CTRL1_REG, 0x6300000); in hikey960_enable_ppll3()
44 mmio_write_32(PMC_NOC_POWER_IDLEREQ_REG, pmc_value); in bus_idle_clear()
63 mmio_write_32(CRG_CLKDIV20_REG, 0x00020002); in set_vivobus_power_up()
64 mmio_write_32(CRG_PEREN0_REG, 0x00001000); in set_vivobus_power_up()
70 mmio_write_32(CRG_CLKDIV5_REG, 0x003f000b); in set_dss_power_up()
72 mmio_write_32(CRG_CLKDIV3_REG, 0xf0001000); in set_dss_power_up()
[all …]
/external/arm-trusted-firmware/plat/intel/soc/common/soc/
Dsocfpga_system_manager.c20 mmio_write_32(SOCFPGA_L4_PER_SCR(NAND_REGISTER), DISABLE_L4_FIREWALL); in enable_ns_peripheral_access()
21 mmio_write_32(SOCFPGA_L4_PER_SCR(NAND_DATA), DISABLE_L4_FIREWALL); in enable_ns_peripheral_access()
23 mmio_write_32(SOCFPGA_L4_SYS_SCR(NAND_ECC), DISABLE_L4_FIREWALL); in enable_ns_peripheral_access()
24 mmio_write_32(SOCFPGA_L4_SYS_SCR(NAND_READ_ECC), DISABLE_L4_FIREWALL); in enable_ns_peripheral_access()
25 mmio_write_32(SOCFPGA_L4_SYS_SCR(NAND_WRITE_ECC), in enable_ns_peripheral_access()
28 mmio_write_32(SOCFPGA_L4_PER_SCR(USB0_REGISTER), DISABLE_L4_FIREWALL); in enable_ns_peripheral_access()
29 mmio_write_32(SOCFPGA_L4_PER_SCR(USB1_REGISTER), DISABLE_L4_FIREWALL); in enable_ns_peripheral_access()
30 mmio_write_32(SOCFPGA_L4_SYS_SCR(USB0_ECC), DISABLE_L4_FIREWALL); in enable_ns_peripheral_access()
31 mmio_write_32(SOCFPGA_L4_SYS_SCR(USB1_ECC), DISABLE_L4_FIREWALL); in enable_ns_peripheral_access()
33 mmio_write_32(SOCFPGA_L4_PER_SCR(SPI_MASTER0), DISABLE_L4_FIREWALL); in enable_ns_peripheral_access()
[all …]
/external/arm-trusted-firmware/plat/mediatek/mt8173/drivers/spm/
Dspm.c96 mmio_write_32(SPM_POWERON_CONFIG_SET, SPM_REGWR_CFG_KEY | SPM_REGWR_EN); in spm_register_init()
98 mmio_write_32(SPM_POWER_ON_VAL0, 0); in spm_register_init()
99 mmio_write_32(SPM_POWER_ON_VAL1, POWER_ON_VAL1_DEF); in spm_register_init()
100 mmio_write_32(SPM_PCM_PWR_IO_EN, 0); in spm_register_init()
102 mmio_write_32(SPM_PCM_CON0, CON0_CFG_KEY | CON0_PCM_SW_RESET); in spm_register_init()
103 mmio_write_32(SPM_PCM_CON0, CON0_CFG_KEY); in spm_register_init()
107 mmio_write_32(SPM_PCM_CON0, CON0_CFG_KEY | CON0_IM_SLEEP_DVS); in spm_register_init()
108 mmio_write_32(SPM_PCM_CON1, CON1_CFG_KEY | CON1_EVENT_LOCK_EN | in spm_register_init()
110 mmio_write_32(SPM_PCM_IM_PTR, 0); in spm_register_init()
111 mmio_write_32(SPM_PCM_IM_LEN, 0); in spm_register_init()
[all …]
Dspm_mcdi.c248 mmio_write_32(SPM_PCM_REG_DATA_INI, PCM_MCDI_HANDSHAKE_SYNC); in spm_mcdi_cpu_wake_up_event()
249 mmio_write_32(SPM_PCM_PWR_IO_EN, PCM_RF_SYNC_R6); in spm_mcdi_cpu_wake_up_event()
250 mmio_write_32(SPM_PCM_PWR_IO_EN, 0); in spm_mcdi_cpu_wake_up_event()
269 mmio_write_32(SPM_SLEEP_CPU_WAKEUP_EVENT, wake_up_event); in spm_mcdi_cpu_wake_up_event()
275 mmio_write_32(SPM_PCM_REG_DATA_INI, PCM_MCDI_UPDATE_INFORM); in spm_mcdi_cpu_wake_up_event()
276 mmio_write_32(SPM_PCM_PWR_IO_EN, PCM_RF_SYNC_R6); in spm_mcdi_cpu_wake_up_event()
277 mmio_write_32(SPM_PCM_PWR_IO_EN, 0); in spm_mcdi_cpu_wake_up_event()
283 mmio_write_32(SPM_PCM_REG_DATA_INI, 0x0); in spm_mcdi_cpu_wake_up_event()
284 mmio_write_32(SPM_PCM_PWR_IO_EN, PCM_RF_SYNC_R6); in spm_mcdi_cpu_wake_up_event()
285 mmio_write_32(SPM_PCM_PWR_IO_EN, 0); in spm_mcdi_cpu_wake_up_event()
[all …]
/external/arm-trusted-firmware/plat/mediatek/mt8183/drivers/emi_mpu/
Demi_mpu.c52 mmio_write_32(EMI_MPU_APC0, 0); in emi_mpu_set_region_protection()
53 mmio_write_32(EMI_MPU_SA0, start); in emi_mpu_set_region_protection()
54 mmio_write_32(EMI_MPU_EA0, end); in emi_mpu_set_region_protection()
55 mmio_write_32(EMI_MPU_APC0, access_permission); in emi_mpu_set_region_protection()
59 mmio_write_32(EMI_MPU_APC1, 0); in emi_mpu_set_region_protection()
60 mmio_write_32(EMI_MPU_SA1, start); in emi_mpu_set_region_protection()
61 mmio_write_32(EMI_MPU_EA1, end); in emi_mpu_set_region_protection()
62 mmio_write_32(EMI_MPU_APC1, access_permission); in emi_mpu_set_region_protection()
66 mmio_write_32(EMI_MPU_APC2, 0); in emi_mpu_set_region_protection()
67 mmio_write_32(EMI_MPU_SA2, start); in emi_mpu_set_region_protection()
[all …]
/external/arm-trusted-firmware/plat/intel/soc/stratix10/soc/
Ds10_clock_manager.c43 mmio_write_32(ALT_CLKMGR_MAINPLL + in config_clkmgr_handoff()
48 mmio_write_32(ALT_CLKMGR_PERPLL + in config_clkmgr_handoff()
60 mmio_write_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_PLLGLOB, in config_clkmgr_handoff()
62 mmio_write_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_FDBCK, in config_clkmgr_handoff()
64 mmio_write_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_VCOCALIB, in config_clkmgr_handoff()
67 mmio_write_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_PLLC0, in config_clkmgr_handoff()
69 mmio_write_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_PLLC1, in config_clkmgr_handoff()
72 mmio_write_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_NOCDIV, in config_clkmgr_handoff()
82 mmio_write_32(ALT_CLKMGR_PERPLL + ALT_CLKMGR_PERPLL_PLLGLOB, in config_clkmgr_handoff()
84 mmio_write_32(ALT_CLKMGR_PERPLL + ALT_CLKMGR_PERPLL_FDBCK, in config_clkmgr_handoff()
[all …]
/external/arm-trusted-firmware/drivers/renesas/rzg/qos/G2M/
Dqos_init_g2m_v10.c75 mmio_write_32(AXI_ADSPLCR0, 0x00000000U); in qos_init_g2m_v10()
76 mmio_write_32(AXI_ADSPLCR1, ADSPLCR0_ADRMODE_DEFAULT | in qos_init_g2m_v10()
79 mmio_write_32(AXI_ADSPLCR2, 0x089A0000U); in qos_init_g2m_v10()
80 mmio_write_32(AXI_ADSPLCR3, 0x00000000U); in qos_init_g2m_v10()
91 mmio_write_32(QOSCTRL_RAS, 0x00000028U); in qos_init_g2m_v10()
92 mmio_write_32(QOSCTRL_FIXTH, 0x000F0005U); in qos_init_g2m_v10()
93 mmio_write_32(QOSCTRL_REGGD, 0x00000000U); in qos_init_g2m_v10()
95 mmio_write_32(QOSCTRL_DANT, 0x00100804U); in qos_init_g2m_v10()
96 mmio_write_32(QOSCTRL_EC, 0x00000000U); in qos_init_g2m_v10()
98 mmio_write_32(QOSCTRL_FSS, 0x000003e8U); in qos_init_g2m_v10()
[all …]
Dqos_init_g2m_v11.c119 mmio_write_32(AXI_ADSPLCR0, 0x00000000U); in qos_init_g2m_v11()
120 mmio_write_32(AXI_ADSPLCR1, ADSPLCR0_ADRMODE_DEFAULT | in qos_init_g2m_v11()
123 mmio_write_32(AXI_ADSPLCR2, 0x00001004U); in qos_init_g2m_v11()
124 mmio_write_32(AXI_ADSPLCR3, 0x00000000U); in qos_init_g2m_v11()
144 mmio_write_32(QOSCTRL_RAS, 0x00000044U); in qos_init_g2m_v11()
146 mmio_write_32(QOSCTRL_DANT, 0x0020100AU); in qos_init_g2m_v11()
147 mmio_write_32(QOSCTRL_INSFC, 0x06330001U); in qos_init_g2m_v11()
148 mmio_write_32(QOSCTRL_RACNT0, 0x02010003U); /* GPU Boost Mode ON */ in qos_init_g2m_v11()
150 mmio_write_32(QOSCTRL_SL_INIT, in qos_init_g2m_v11()
154 mmio_write_32(QOSCTRL_REF_ARS, in qos_init_g2m_v11()
[all …]
Dqos_init_g2m_v30.c119 mmio_write_32(AXI_ADSPLCR0, 0x00000000U); in qos_init_g2m_v30()
120 mmio_write_32(AXI_ADSPLCR1, ADSPLCR0_ADRMODE_DEFAULT | in qos_init_g2m_v30()
123 mmio_write_32(AXI_ADSPLCR2, 0x00001004U); in qos_init_g2m_v30()
124 mmio_write_32(AXI_ADSPLCR3, 0x00000000U); in qos_init_g2m_v30()
144 mmio_write_32(QOSCTRL_RAS, 0x00000044U); in qos_init_g2m_v30()
146 mmio_write_32(QOSCTRL_DANT, 0x0020100AU); in qos_init_g2m_v30()
147 mmio_write_32(QOSCTRL_FSS, 0x0000000AU); in qos_init_g2m_v30()
148 mmio_write_32(QOSCTRL_INSFC, 0x06330001U); in qos_init_g2m_v30()
149 mmio_write_32(QOSCTRL_EARLYR, 0x00000001U); in qos_init_g2m_v30()
150 mmio_write_32(QOSCTRL_RACNT0, 0x02010003U); /* GPU Boost Mode ON */ in qos_init_g2m_v30()
[all …]
/external/arm-trusted-firmware/plat/rockchip/rk3288/drivers/secure/
Dsecure.c21 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(21), in sgrf_ddr_rgn_global_bypass()
25 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(21), in sgrf_ddr_rgn_global_bypass()
66 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(6 + (rgn * 2)), in sgrf_ddr_rgn_config()
70 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(6 + (rgn * 2) + 1), in sgrf_ddr_rgn_config()
74 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(6 + (rgn * 2)), in sgrf_ddr_rgn_config()
78 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(6 + (rgn * 2)), in sgrf_ddr_rgn_config()
84 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(0), SGRF_PCLK_WDT_GATE); in secure_watchdog_gate()
89 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(0), SGRF_PCLK_WDT_UNGATE); in secure_watchdog_ungate()
94 mmio_write_32(STIMER1_BASE + TIMER_CONTROL_REG, 0); in sram_secure_timer_init()
96 mmio_write_32(STIMER1_BASE + TIMER_LOAD_COUNT0, 0xffffffff); in sram_secure_timer_init()
[all …]
/external/arm-trusted-firmware/plat/rockchip/rk3399/drivers/secure/
Dsecure.c21 mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON0_16(16), in sgrf_ddr_rgn_global_bypass()
25 mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON0_16(16), in sgrf_ddr_rgn_global_bypass()
74 mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON0_16(rgn), in sgrf_ddr_rgn_config()
78 mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON0_16(rgn + 8), in sgrf_ddr_rgn_config()
81 mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON0_16(16), in sgrf_ddr_rgn_config()
92 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(3), in secure_watchdog_gate()
104 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(3), in secure_watchdog_ungate()
111 mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_END_COUNT0, 0xffffffff); in sram_secure_timer_init()
112 mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_END_COUNT1, 0xffffffff); in sram_secure_timer_init()
114 mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_INIT_COUNT0, 0x0); in sram_secure_timer_init()
[all …]
/external/arm-trusted-firmware/plat/rockchip/rk3328/drivers/pmu/
Dpmu.c63 mmio_write_32(PMU_BASE + PMU_CPUAPM_CON(cpu_id), in cpus_power_domain_on()
68 mmio_write_32(PMU_BASE + PMU_CPUAPM_CON(cpu_id), in cpus_power_domain_on()
79 mmio_write_32(PMU_BASE + PMU_CPUAPM_CON(cpu_id), in cpus_power_domain_on()
98 mmio_write_32(PMU_BASE + PMU_CPUAPM_CON(cpu_id), in cpus_power_domain_off()
106 mmio_write_32(PMU_BASE + PMU_CPUAPM_CON(cpu_id), in cpus_power_domain_off()
179 mmio_write_32(PMU_BASE + PMU_CPUAPM_CON(cpu_id), CORES_PM_DISABLE); in rockchip_soc_cores_pwr_dm_on_finish()
188 mmio_write_32(PMU_BASE + PMU_CPUAPM_CON(cpu_id), CORES_PM_DISABLE); in rockchip_soc_cores_pwr_dm_resume()
195 mmio_write_32(CRU_BASE + CRU_CRU_MODE, PLL_SLOW_MODE(CPLL_ID)); in rockchip_soc_soft_reset()
196 mmio_write_32(CRU_BASE + CRU_CRU_MODE, PLL_SLOW_MODE(GPLL_ID)); in rockchip_soc_soft_reset()
197 mmio_write_32(CRU_BASE + CRU_CRU_MODE, PLL_SLOW_MODE(NPLL_ID)); in rockchip_soc_soft_reset()
[all …]
/external/arm-trusted-firmware/drivers/renesas/common/pwrc/
Dpwrc.c205 mmio_write_32(reg_cpumcr, 0); in scu_power_up()
213 mmio_write_32(reg_pwron, 1); in scu_power_up()
218 mmio_write_32(RCAR_SYSCISR, sysc_reg_bit); in scu_power_up()
241 mmio_write_32(RCAR_CPGWPR, ~on_data); in rcar_pwrc_cpuon()
242 mmio_write_32(on_reg, on_data); in rcar_pwrc_cpuon()
243 mmio_write_32(res_reg, res_data & (~(1 << (3 - cpu)))); in rcar_pwrc_cpuon()
263 mmio_write_32(RCAR_CPGWPR, ~CPU_PWR_OFF); in rcar_pwrc_cpuoff()
264 mmio_write_32(reg + cpu * 0x0010, CPU_PWR_OFF); in rcar_pwrc_cpuoff()
284 mmio_write_32(reg, ~((uint32_t) 1 << shift_irq) & in rcar_pwrc_enable_interrupt_wakeup()
304 mmio_write_32(reg, ((uint32_t) 1 << shift_irq) | in rcar_pwrc_disable_interrupt_wakeup()
[all …]
/external/arm-trusted-firmware/plat/rockchip/rk3368/drivers/soc/
Dsoc.c70 mmio_write_32(STIMER1_BASE + TIMER_LOADE_COUNT0, 0xffffffff); in secure_timer_init()
71 mmio_write_32(STIMER1_BASE + TIMER_LOADE_COUNT1, 0xffffffff); in secure_timer_init()
74 mmio_write_32(STIMER1_BASE + TIMER_CONTROL_REG, TIMER_EN); in secure_timer_init()
80 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(5), SGRF_SOC_CON_NS); in sgrf_init()
81 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(6), SGRF_SOC_CON7_BITS); in sgrf_init()
82 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(7), SGRF_SOC_CON_NS); in sgrf_init()
85 mmio_write_32(SGRF_BASE + SGRF_BUSDMAC_CON(0), SGRF_BUSDMAC_CON0_NS); in sgrf_init()
86 mmio_write_32(SGRF_BASE + SGRF_BUSDMAC_CON(1), SGRF_BUSDMAC_CON1_NS); in sgrf_init()
90 mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(1), in sgrf_init()
93 mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(4), in sgrf_init()
[all …]
/external/arm-trusted-firmware/plat/imx/imx8m/imx8mp/
Dgpc.c131 mmio_write_32(IMX_HDMI_CTL_BASE + TX_CONTROL1, 0x22018); in imx_noc_qos()
132 mmio_write_32(IMX_HDMI_CTL_BASE + TX_CONTROL1, 0x22010); in imx_noc_qos()
137 mmio_write_32(IMX_HDMI_CTL_BASE + TX_CONTROL0, hurry); in imx_noc_qos()
142 mmio_write_32(IMX_MEDIAMIX_CTL_BASE + RSTn_CSR, 0x1FFFFFF); in imx_noc_qos()
143 mmio_write_32(IMX_MEDIAMIX_CTL_BASE + CLK_EN_CSR, 0x1FFFFFF); in imx_noc_qos()
144 mmio_write_32(IMX_MEDIAMIX_CTL_BASE + RST_DIV, 0x40030000); in imx_noc_qos()
149 mmio_write_32(IMX_MEDIAMIX_CTL_BASE + LCDIF_ARCACHE_CTRL, hurry); in imx_noc_qos()
153 mmio_write_32(IMX_MEDIAMIX_CTL_BASE + ISI_CACHE_CTRL, hurry); in imx_noc_qos()
163 mmio_write_32(IMX_NOC_BASE + offset + 0x8, noc_setting[i].prioriy); in imx_noc_qos()
164 mmio_write_32(IMX_NOC_BASE + offset + 0xc, noc_setting[i].mode); in imx_noc_qos()
[all …]
/external/arm-trusted-firmware/plat/intel/soc/agilex/soc/
Dagilex_clock_manager.c58 mmio_write_32(pll_mem_offset, val); in pll_source_sync_config()
79 mmio_write_32(pll_mem_offset, val); in pll_source_sync_read()
104 mmio_write_32(CLKMGR_MAINPLL + CLKMGR_MAINPLL_BYPASS, 0x7); in config_clkmgr_handoff()
108 mmio_write_32(CLKMGR_PERPLL + CLKMGR_PERPLL_BYPASS, 0x7f); in config_clkmgr_handoff()
132 mmio_write_32(CLKMGR_MAINPLL + CLKMGR_MAINPLL_PLLGLOB, in config_clkmgr_handoff()
135 mmio_write_32(CLKMGR_MAINPLL + CLKMGR_MAINPLL_FDBCK, in config_clkmgr_handoff()
137 mmio_write_32(CLKMGR_MAINPLL + CLKMGR_MAINPLL_VCOCALIB, in config_clkmgr_handoff()
140 mmio_write_32(CLKMGR_MAINPLL + CLKMGR_MAINPLL_PLLC0, in config_clkmgr_handoff()
142 mmio_write_32(CLKMGR_MAINPLL + CLKMGR_MAINPLL_PLLC1, in config_clkmgr_handoff()
144 mmio_write_32(CLKMGR_MAINPLL + CLKMGR_MAINPLL_PLLC2, in config_clkmgr_handoff()
[all …]
/external/arm-trusted-firmware/plat/imx/imx8m/imx8mn/
Dgpc.c31 mmio_write_32(IMX_GPC_BASE + IMR1_CORE0_A53 + i * 4, ~0x0); in imx_gpc_init()
32 mmio_write_32(IMX_GPC_BASE + IMR1_CORE1_A53 + i * 4, ~0x0); in imx_gpc_init()
33 mmio_write_32(IMX_GPC_BASE + IMR1_CORE2_A53 + i * 4, ~0x0); in imx_gpc_init()
34 mmio_write_32(IMX_GPC_BASE + IMR1_CORE3_A53 + i * 4, ~0x0); in imx_gpc_init()
35 mmio_write_32(IMX_GPC_BASE + IMR1_CORE0_M4 + i * 4, ~0x0); in imx_gpc_init()
43 mmio_write_32(IMX_GPC_BASE + LPCR_A53_BSC, val); in imx_gpc_init()
50 mmio_write_32(IMX_GPC_BASE + PGC_CPU_0_1_MAPPING, 0xffff); in imx_gpc_init()
59 mmio_write_32(IMX_GPC_BASE + COREx_PGC_PCR(0) + 0x4, 0x401); in imx_gpc_init()
60 mmio_write_32(IMX_GPC_BASE + COREx_PGC_PCR(1) + 0x4, 0x401); in imx_gpc_init()
61 mmio_write_32(IMX_GPC_BASE + COREx_PGC_PCR(2) + 0x4, 0x401); in imx_gpc_init()
[all …]
/external/arm-trusted-firmware/plat/imx/imx8m/imx8mm/
Dgpc.c29 mmio_write_32(IMX_GPC_BASE + IMR1_CORE0_A53 + i * 4, ~0x0); in imx_gpc_init()
30 mmio_write_32(IMX_GPC_BASE + IMR1_CORE1_A53 + i * 4, ~0x0); in imx_gpc_init()
31 mmio_write_32(IMX_GPC_BASE + IMR1_CORE2_A53 + i * 4, ~0x0); in imx_gpc_init()
32 mmio_write_32(IMX_GPC_BASE + IMR1_CORE3_A53 + i * 4, ~0x0); in imx_gpc_init()
33 mmio_write_32(IMX_GPC_BASE + IMR1_CORE0_M4 + i * 4, ~0x0); in imx_gpc_init()
41 mmio_write_32(IMX_GPC_BASE + LPCR_A53_BSC, val); in imx_gpc_init()
48 mmio_write_32(IMX_GPC_BASE + PGC_CPU_0_1_MAPPING, 0xffff); in imx_gpc_init()
57 mmio_write_32(IMX_GPC_BASE + COREx_PGC_PCR(0) + 0x4, 0x81); in imx_gpc_init()
58 mmio_write_32(IMX_GPC_BASE + COREx_PGC_PCR(1) + 0x4, 0x81); in imx_gpc_init()
59 mmio_write_32(IMX_GPC_BASE + COREx_PGC_PCR(2) + 0x4, 0x81); in imx_gpc_init()
[all …]
/external/arm-trusted-firmware/plat/rockchip/px30/drivers/secure/
Dsecure.c39 mmio_write_32(FIREWALL_DDR_BASE + in secure_ddr_region()
46 mmio_write_32(FIREWALL_DDR_BASE + in secure_ddr_region()
52 mmio_write_32(STIMER_CHN_BASE(1) + TIMER_CONTROL_REG, in secure_timer_init()
55 mmio_write_32(STIMER_CHN_BASE(1) + TIMER_LOAD_COUNT0, 0xffffffff); in secure_timer_init()
56 mmio_write_32(STIMER_CHN_BASE(1) + TIMER_LOAD_COUNT1, 0xffffffff); in secure_timer_init()
59 mmio_write_32(STIMER_CHN_BASE(1) + TIMER_CONTROL_REG, in secure_timer_init()
84 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(4), SGRF_SLV_S_ALL_NS); in sgrf_init()
85 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(5), SGRF_SLV_S_ALL_NS); in sgrf_init()
86 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(6), SGRF_SLV_S_ALL_NS); in sgrf_init()
87 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(7), SGRF_SLV_S_ALL_NS); in sgrf_init()
[all …]
/external/arm-trusted-firmware/plat/mediatek/common/drivers/uart/
Duart.c30 mmio_write_32(UART_LCR(base), UART_LCR_MODE_B); in mt_uart_restore()
31 mmio_write_32(UART_EFR(base), uart->registers.efr); in mt_uart_restore()
32 mmio_write_32(UART_LCR(base), uart->registers.lcr); in mt_uart_restore()
33 mmio_write_32(UART_FCR(base), uart->registers.fcr); in mt_uart_restore()
36 mmio_write_32(UART_HIGHSPEED(base), uart->registers.highspeed); in mt_uart_restore()
37 mmio_write_32(UART_FRACDIV_L(base), uart->registers.fracdiv_l); in mt_uart_restore()
38 mmio_write_32(UART_FRACDIV_M(base), uart->registers.fracdiv_m); in mt_uart_restore()
39 mmio_write_32(UART_LCR(base), in mt_uart_restore()
41 mmio_write_32(UART_DLL(base), uart->registers.dll); in mt_uart_restore()
42 mmio_write_32(UART_DLH(base), uart->registers.dlh); in mt_uart_restore()
[all …]

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