| /external/arm-trusted-firmware/drivers/renesas/rzg/qos/G2M/ |
| D | qos_init_g2m_v30.c | 145 mmio_write_64(QOSCTRL_DANN, 0x0404020002020201UL); in qos_init_g2m_v30()
162 mmio_write_64(QOSBW_FIX_QOS_BANK0 + i * 8U, mstat_fix[i]); in qos_init_g2m_v30()
163 mmio_write_64(QOSBW_FIX_QOS_BANK1 + i * 8U, mstat_fix[i]); in qos_init_g2m_v30()
166 mmio_write_64(QOSBW_BE_QOS_BANK0 + i * 8U, mstat_be[i]); in qos_init_g2m_v30()
167 mmio_write_64(QOSBW_BE_QOS_BANK1 + i * 8U, mstat_be[i]); in qos_init_g2m_v30()
171 mmio_write_64(QOSWT_FIX_WTQOS_BANK0 + i * 8U, qoswt_fix[i]); in qos_init_g2m_v30()
172 mmio_write_64(QOSWT_FIX_WTQOS_BANK1 + i * 8U, qoswt_fix[i]); in qos_init_g2m_v30()
175 mmio_write_64(QOSWT_BE_WTQOS_BANK0 + i * 8U, qoswt_be[i]); in qos_init_g2m_v30()
176 mmio_write_64(QOSWT_BE_WTQOS_BANK1 + i * 8U, qoswt_be[i]); in qos_init_g2m_v30()
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| D | qos_init_g2m_v11.c | 145 mmio_write_64(QOSCTRL_DANN, 0x0404020002020201UL); in qos_init_g2m_v11()
161 mmio_write_64(QOSBW_FIX_QOS_BANK0 + i * 8U, mstat_fix[i]); in qos_init_g2m_v11()
162 mmio_write_64(QOSBW_FIX_QOS_BANK1 + i * 8U, mstat_fix[i]); in qos_init_g2m_v11()
165 mmio_write_64(QOSBW_BE_QOS_BANK0 + i * 8U, mstat_be[i]); in qos_init_g2m_v11()
166 mmio_write_64(QOSBW_BE_QOS_BANK1 + i * 8U, mstat_be[i]); in qos_init_g2m_v11()
170 mmio_write_64(QOSWT_FIX_WTQOS_BANK0 + i * 8U, qoswt_fix[i]); in qos_init_g2m_v11()
171 mmio_write_64(QOSWT_FIX_WTQOS_BANK1 + i * 8U, qoswt_fix[i]); in qos_init_g2m_v11()
174 mmio_write_64(QOSWT_BE_WTQOS_BANK0 + i * 8U, qoswt_be[i]); in qos_init_g2m_v11()
175 mmio_write_64(QOSWT_BE_WTQOS_BANK1 + i * 8U, qoswt_be[i]); in qos_init_g2m_v11()
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| D | qos_init_g2m_v10.c | 94 mmio_write_64(QOSCTRL_DANN, 0x0101010102020201UL); in qos_init_g2m_v10()
97 mmio_write_64(QOSCTRL_EMS, 0x0000000000000000UL); in qos_init_g2m_v10()
112 mmio_write_64(QOSBW_FIX_QOS_BANK0 + i * 8U, mstat_fix[i]); in qos_init_g2m_v10()
113 mmio_write_64(QOSBW_FIX_QOS_BANK1 + i * 8U, mstat_fix[i]); in qos_init_g2m_v10()
116 mmio_write_64(QOSBW_BE_QOS_BANK0 + i * 8U, mstat_be[i]); in qos_init_g2m_v10()
117 mmio_write_64(QOSBW_BE_QOS_BANK1 + i * 8U, mstat_be[i]); in qos_init_g2m_v10()
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| /external/arm-trusted-firmware/drivers/arm/gic/v3/ |
| D | gicv3_private.h | 81 mmio_write_64((base) + GICD_OFFSET_64(REG, (id)), (val))
631 mmio_write_64(base + GICR_PROPBASER, val); in gicr_write_propbaser()
644 mmio_write_64(base + GICR_PENDBASER, val); in gicr_write_pendbaser()
667 mmio_write_64(base + GITS_CBASER, val); in gits_write_cbaser()
677 mmio_write_64(base + GITS_CWRITER, val); in gits_write_cwriter()
691 mmio_write_64(base + GITS_BASER + (8U * its_table_id), val); in gits_write_baser()
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| D | gic600_multichip_private.h | 104 mmio_write_64(base + (GICD_CHIPR + (8U * n)), val); in write_gicd_chipr_n()
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| /external/arm-trusted-firmware/plat/intel/soc/agilex/ |
| D | bl31_plat_setup.c | 42 mmio_write_64(PLAT_SEC_ENTRY, PLAT_SEC_WARM_ENTRY); in bl31_early_platform_setup2()
113 mmio_write_64(PLAT_CPU_RELEASE_ADDR, in bl31_platform_setup()
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| /external/arm-trusted-firmware/plat/intel/soc/stratix10/ |
| D | bl31_plat_setup.c | 50 mmio_write_64(PLAT_SEC_ENTRY, PLAT_SEC_WARM_ENTRY); in bl31_early_platform_setup2()
121 mmio_write_64(PLAT_CPU_RELEASE_ADDR, in bl31_platform_setup()
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| /external/arm-trusted-firmware/plat/intel/soc/common/ |
| D | socfpga_psci.c | 47 mmio_write_64(PLAT_CPUID_RELEASE, cpu_id); in socfpga_pwr_domain_on()
222 mmio_write_64(PLAT_SEC_ENTRY, sec_entrypoint); in plat_setup_psci_ops()
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| /external/arm-trusted-firmware/plat/rpi/common/ |
| D | rpi3_pm.c | 149 mmio_write_64(hold_base, PLAT_RPI3_TM_HOLD_STATE_GO); in rpi3_pwr_domain_on()
191 mmio_write_64(hold_base, PLAT_RPI3_TM_HOLD_STATE_BSP_OFF); in rpi3_pwr_down_wfi()
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| /external/arm-trusted-firmware/include/lib/ |
| D | mmio.h | 49 static inline void mmio_write_64(uintptr_t addr, uint64_t value) in mmio_write_64() function
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| /external/arm-trusted-firmware/plat/hisilicon/hikey/ |
| D | hisi_pwrc.c | 37 mmio_write_64((uintptr_t)(core_entry + i), entry_point); in hisi_pwrc_set_core_bx_addr()
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| /external/arm-trusted-firmware/plat/arm/board/morello/ |
| D | morello_bl31_setup.c | 71 mmio_write_64((dst + i), mmio_read_64(src + i)); in copy_bl33()
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| /external/arm-trusted-firmware/plat/socionext/uniphier/ |
| D | uniphier_psci.c | 42 mmio_write_64(uniphier_rom_rsv_base + UNIPHIER_ROM_RSV0, in uniphier_psci_pwr_domain_on()
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| /external/arm-trusted-firmware/plat/amlogic/axg/ |
| D | axg_pm.c | 34 mmio_write_64(cpu_mailbox_addr, value); in axg_pm_set_reset_addr()
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| /external/arm-trusted-firmware/plat/amlogic/gxbb/ |
| D | gxbb_pm.c | 35 mmio_write_64(cpu_mailbox_addr, value); in gxbb_program_mailbox()
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| /external/arm-trusted-firmware/plat/amlogic/g12a/ |
| D | g12a_pm.c | 35 mmio_write_64(cpu_mailbox_addr, value); in g12a_pm_set_reset_addr()
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| /external/arm-trusted-firmware/plat/amlogic/gxl/ |
| D | gxl_pm.c | 35 mmio_write_64(cpu_mailbox_addr, value); in gxl_pm_set_reset_addr()
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| /external/arm-trusted-firmware/plat/arm/board/n1sdp/ |
| D | n1sdp_bl31_setup.c | 163 mmio_write_64((dst + i), mmio_read_64(src + i)); in copy_bl33()
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| /external/arm-trusted-firmware/plat/brcm/board/stingray/src/ |
| D | iommu.c | 497 mmio_write_64((uintptr_t) (ARM_SMMU_CB_BASE(smmu) + in arm_smmu_create_identity_map()
504 mmio_write_64((uintptr_t) (ARM_SMMU_CB_BASE(smmu) + in arm_smmu_create_identity_map()
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| D | brcm_pm_ops.c | 403 mmio_write_64(CRMU_CFG_BASE + offsetof(M0CFG, core_cfg.rvbar), in plat_setup_psci_ops()
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| /external/arm-trusted-firmware/include/lib/extensions/ |
| D | ras_arch.h | 227 mmio_write_64(base + ERR_STATUS(idx), status); in ser_set_status()
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| /external/arm-trusted-firmware/drivers/arm/ccn/ |
| D | ccn.c | 59 mmio_write_64(region_base + register_offset, value); in ccn_reg_write()
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| /external/arm-trusted-firmware/plat/mediatek/mt8183/ |
| D | plat_pm.c | 131 mmio_write_64(MCUCFG_BASE + 0x2200, 0x2092c820); in mp1_L2_desel_config()
|