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/external/llvm-project/llvm/test/CodeGen/AArch64/
Ddp-3source.ll115 ; CHECK: mneg {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
123 ; CHECK: mneg {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
176 ; CHECK: mneg {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
Daarch64-fix-cortex-a53-835769.ll129 ; FIXME-CHECK-NEXT: mneg
131 ; FIXME-CHECK-NOWORKAROUND-NEXT: mneg
146 ; FIXME-CHECK-NEXT: mneg
148 ; FIXME-CHECK-NOWORKAROUND-NEXT: mneg
/external/llvm/test/CodeGen/AArch64/
Ddp-3source.ll115 ; CHECK: mneg {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
123 ; CHECK: mneg {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
176 ; CHECK: mneg {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
Daarch64-fix-cortex-a53-835769.ll129 ; FIXME-CHECK-NEXT: mneg
131 ; FIXME-CHECK-NOWORKAROUND-NEXT: mneg
146 ; FIXME-CHECK-NEXT: mneg
148 ; FIXME-CHECK-NOWORKAROUND-NEXT: mneg
/external/capstone/suite/MC/AArch64/
Dbasic-a64-instructions.s.cs612 0xa4,0xfc,0x06,0x1b = mneg w4, w5, w6
617 0xa4,0xfc,0x06,0x9b = mneg x4, x5, x6
654 0xd5,0xfe,0x17,0x1b = mneg w21, w22, w23
655 0x1f,0xff,0x19,0x1b = mneg wzr, w24, w25
656 0xfa,0xff,0x1b,0x1b = mneg w26, wzr, w27
657 0xbc,0xff,0x1f,0x1b = mneg w28, w29, wzr
/external/llvm-project/llvm/test/MC/AArch64/
Dbasic-a64-instructions.s1662 mneg w21, w22, w23
1663 mneg wzr, w24, w25
1664 mneg w26, wzr, w27
1665 mneg w28, w29, wzr
/external/llvm-project/llvm/test/tools/llvm-mca/AArch64/Cortex/
DA55-basic-instructions.s508 mneg w4, w5, w6 label
513 mneg x4, x5, x6 label
536 mneg w21, w22, w23 label
1825 # CHECK-NEXT: 1 4 1.00 mneg w4, w5, w6
1830 # CHECK-NEXT: 1 4 1.00 mneg x4, x5, x6
1853 # CHECK-NEXT: 1 4 1.00 mneg w21, w22, w23
3008 … - - - - - - - - - - 1.00 - mneg w4, w5, w6
3013 … - - - - - - - - - - 1.00 - mneg x4, x5, x6
3036 … - - - - - - - - - 1.00 - mneg w21, w22, w23
/external/llvm/test/MC/AArch64/
Dbasic-a64-instructions.s1679 mneg w21, w22, w23
1680 mneg wzr, w24, w25
1681 mneg w26, wzr, w27
1682 mneg w28, w29, wzr
/external/vixl/test/aarch64/
Dtest-disasm-aarch64.cc423 COMPARE(mneg(w0, w1, w2), "mneg w0, w1, w2"); in TEST()
424 COMPARE(mneg(x3, x4, x5), "mneg x3, x4, x5"); in TEST()
425 COMPARE(mneg(w30, w0, w1), "mneg w30, w0, w1"); in TEST()
426 COMPARE(mneg(x30, x0, x1), "mneg x30, x0, x1"); in TEST()
Dtest-trace-aarch64.cc241 __ mneg(w5, w6, w7); in GenerateTestSequenceBase() local
242 __ mneg(x8, x9, x10); in GenerateTestSequenceBase() local
Dtest-cpu-features-aarch64.cc367 TEST_NONE(mneg_0, mneg(w0, w1, w2))
368 TEST_NONE(mneg_1, mneg(x0, x1, x2))
/external/llvm/test/MC/Disassembler/AArch64/
Dbasic-a64-instructions.txt1148 # CHECK: mneg w4, w5, w6
1159 # CHECK: mneg x4, x5, x6
1245 # CHECK: mneg w21, w22, w23
1246 # CHECK: mneg wzr, w24, w25
1247 # CHECK: mneg w26, wzr, w27
1248 # CHECK: mneg w28, w29, wzr
/external/llvm-project/llvm/test/MC/Disassembler/AArch64/
Dbasic-a64-instructions.txt1135 # CHECK: mneg w4, w5, w6
1146 # CHECK: mneg x4, x5, x6
1232 # CHECK: mneg w21, w22, w23
1233 # CHECK: mneg wzr, w24, w25
1234 # CHECK: mneg w26, wzr, w27
1235 # CHECK: mneg w28, w29, wzr
/external/vixl/test/test-trace-reference/
Dlog-disasm-colour185 0x~~~~~~~~~~~~~~~~ 1b07fcc5 mneg w5, w6, w7
186 0x~~~~~~~~~~~~~~~~ 9b0afd28 mneg x8, x9, x10
Dlog-disasm185 0x~~~~~~~~~~~~~~~~ 1b07fcc5 mneg w5, w6, w7
186 0x~~~~~~~~~~~~~~~~ 9b0afd28 mneg x8, x9, x10
Dlog-cpufeatures-custom185 0x~~~~~~~~~~~~~~~~ 1b07fcc5 mneg w5, w6, w7
186 0x~~~~~~~~~~~~~~~~ 9b0afd28 mneg x8, x9, x10
Dlog-cpufeatures-colour185 0x~~~~~~~~~~~~~~~~ 1b07fcc5 mneg w5, w6, w7
186 0x~~~~~~~~~~~~~~~~ 9b0afd28 mneg x8, x9, x10
Dlog-cpufeatures185 0x~~~~~~~~~~~~~~~~ 1b07fcc5 mneg w5, w6, w7
186 0x~~~~~~~~~~~~~~~~ 9b0afd28 mneg x8, x9, x10
/external/vixl/src/aarch64/
Dassembler-aarch64.h964 void mneg(const Register& rd, const Register& rn, const Register& rm);
Dassembler-aarch64.cc912 void Assembler::mneg(const Register& rd, in mneg() function in vixl::aarch64::Assembler
Dmacro-assembler-aarch64.h2078 mneg(rd, rn, rm); in Mneg()
/external/llvm/lib/Target/AArch64/
DAArch64InstrInfo.td789 def : MulAccumWAlias<"mneg", MSUBWrrr>;
790 def : MulAccumXAlias<"mneg", MSUBXrrr>;
/external/capstone/arch/AArch64/
DAArch64GenAsmWriter.inc10200 AsmString = "mneg $\x01, $\x02, $\x03";
10214 AsmString = "mneg $\x01, $\x02, $\x03";
/external/vixl/doc/aarch64/
Dsupported-instructions-aarch64.md1913 void mneg(const Register& rd, const Register& rn, const Register& rm)
/external/llvm-project/llvm/lib/Target/AArch64/
DAArch64InstrInfo.td1530 def : MulAccumWAlias<"mneg", MSUBWrrr>;
1531 def : MulAccumXAlias<"mneg", MSUBXrrr>;

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