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Searched refs:movn (Results 1 – 25 of 210) sorted by relevance

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/external/llvm-project/lld/test/ELF/
Daarch64-movw-error.s7 movn x0, #:abs_g0:zero+0x10000 label
9 movn x0, #:abs_g1:zero+0x100000000 label
11 movn x0, #:abs_g2:zero+0x1000000000000 label
13 movn x0, #:abs_g0_s:zero+0x10000 label
15 movn x0, #:abs_g1_s:zero+0x100000000 label
17 movn x0, #:abs_g2_s:zero+0x1000000000000 label
19 movn x0, #:abs_g0_s:zero-0x10001 label
21 movn x0, #:abs_g1_s:zero-0x100010000 label
23 movn x0, #:abs_g2_s:zero-0x1000100000000 label
26 movn x0, #:prel_g0:.+0x10000 label
[all …]
/external/llvm-project/llvm/test/MC/AArch64/
Dtls-relocs.s7 movn x2, #:dtprel_g2:var
9 movn x4, #:dtprel_g2:var
29 movn x6, #:dtprel_g1:var
31 movn w8, #:dtprel_g1:var
61 movn x12, #:dtprel_g0:var
63 movn w14, #:dtprel_g0:var
219 movn x4, #:tprel_g2:var
231 movn x6, #:tprel_g1:var
233 movn w8, #:tprel_g1:var
263 movn x12, #:tprel_g0:var
[all …]
Darm64-aliases.s166 movn x0, #0
167 movn x0, #0, lsl #16
168 movn x0, #0, lsl #32
169 movn x0, #0, lsl #48
170 movn w0, #0
171 movn w0, #0, lsl #16
173 ; CHECK: movn x0, #0x0, lsl #16
174 ; CHECK: movn x0, #0x0, lsl #32
175 ; CHECK: movn x0, #0x0, lsl #48
177 ; CHECK: movn w0, #0x0, lsl #16
[all …]
Delf-reloc-movw.s17 movn x17, #:abs_g0_s:some_label
20 movn x19, #:abs_g1_s:some_label
23 movn x19, #:abs_g2_s:some_label
26 movn x19, #:abs_g2_s:some_label - 20 + 10
Darm64-tls-relocs.s43 movn x4, #:tprel_g2:var
54 movn x6, #:tprel_g1:var
80 movn x12, #:tprel_g0:var
176 movn x4, #:dtprel_g2:var
187 movn x6, #:dtprel_g1:var
213 movn x12, #:dtprel_g0:var
/external/llvm/test/MC/AArch64/
Dtls-relocs.s7 movn x2, #:dtprel_g2:var
9 movn x4, #:dtprel_g2:var
29 movn x6, #:dtprel_g1:var
31 movn w8, #:dtprel_g1:var
61 movn x12, #:dtprel_g0:var
63 movn w14, #:dtprel_g0:var
219 movn x4, #:tprel_g2:var
231 movn x6, #:tprel_g1:var
233 movn w8, #:tprel_g1:var
263 movn x12, #:tprel_g0:var
[all …]
Darm64-aliases.s166 movn x0, #0
167 movn x0, #0, lsl #16
168 movn x0, #0, lsl #32
169 movn x0, #0, lsl #48
170 movn w0, #0
171 movn w0, #0, lsl #16
173 ; CHECK: movn x0, #0x0, lsl #16
174 ; CHECK: movn x0, #0x0, lsl #32
175 ; CHECK: movn x0, #0x0, lsl #48
177 ; CHECK: movn w0, #0x0, lsl #16
[all …]
Darm64-tls-relocs.s44 movn x4, #:tprel_g2:var
55 movn x6, #:tprel_g1:var
81 movn x12, #:tprel_g0:var
168 movn x4, #:dtprel_g2:var
179 movn x6, #:dtprel_g1:var
205 movn x12, #:dtprel_g0:var
Delf-reloc-movw.s17 movn x17, #:abs_g0_s:some_label
20 movn x19, #:abs_g1_s:some_label
23 movn x19, #:abs_g2_s:some_label
/external/llvm-project/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/
Dselect.ll9 ; MIPS32-NEXT: movn $2, $5, $1
22 ; MIPS32-NEXT: movn $2, $5, $1
35 ; MIPS32-NEXT: movn $2, $5, $1
48 ; MIPS32-NEXT: movn $2, $5, $1
64 ; MIPS32-NEXT: movn $2, $6, $1
82 ; MIPS32-NEXT: movn $2, $6, $1
83 ; MIPS32-NEXT: movn $3, $7, $1
97 ; MIPS32-NEXT: movn.d $f0, $f2, $1
115 ; MIPS32-NEXT: movn.s $f0, $f1, $1
129 ; MIPS32-NEXT: movn $1, $2, $3
[all …]
Dcttz.ll40 ; MIPS32-NEXT: movn $2, $1, $4
63 ; MIPS32-NEXT: movn $2, $1, $3
93 ; MIPS32-NEXT: movn $2, $6, $7
104 ; MIPS32-NEXT: movn $2, $1, $4
105 ; MIPS32-NEXT: movn $3, $1, $4
/external/llvm-project/llvm/test/CodeGen/Mips/llvm-ir/
Dashr.ll303 ; MIPS32-NEXT: movn $3, $2, $1
306 ; MIPS32-NEXT: movn $2, $4, $1
317 ; 32R2-NEXT: movn $3, $2, $1
320 ; 32R2-NEXT: movn $2, $4, $1
369 ; MMR3-NEXT: movn $3, $2, $5
372 ; MMR3-NEXT: movn $2, $1, $5
522 ; MIPS32-NEXT: movn $8, $zero, $12
523 ; MIPS32-NEXT: movn $1, $10, $13
533 ; MIPS32-NEXT: movn $1, $8, $14
539 ; MIPS32-NEXT: movn $1, $gp, $25
[all …]
Dlshr.ll305 ; MIPS32-NEXT: movn $3, $2, $1
307 ; MIPS32-NEXT: movn $2, $zero, $1
318 ; MIPS32R2-NEXT: movn $3, $2, $1
320 ; MIPS32R2-NEXT: movn $2, $zero, $1
371 ; MMR3-NEXT: movn $3, $2, $4
374 ; MMR3-NEXT: movn $2, $5, $4
520 ; MIPS32-NEXT: movn $1, $zero, $11
528 ; MIPS32-NEXT: movn $3, $13, $14
538 ; MIPS32-NEXT: movn $1, $8, $15
540 ; MIPS32-NEXT: movn $1, $3, $25
[all …]
Dshl.ll365 ; MIPS32-NEXT: movn $2, $3, $1
367 ; MIPS32-NEXT: movn $3, $zero, $1
378 ; MIPS32R2-NEXT: movn $2, $3, $1
380 ; MIPS32R2-NEXT: movn $3, $zero, $1
431 ; MMR3-NEXT: movn $2, $3, $4
434 ; MMR3-NEXT: movn $3, $5, $4
593 ; MIPS32-NEXT: movn $2, $zero, $10
601 ; MIPS32-NEXT: movn $3, $12, $13
611 ; MIPS32-NEXT: movn $2, $3, $14
613 ; MIPS32-NEXT: movn $2, $15, $25
[all …]
Dselect-int.ll47 ; CMOV: movn $6, $5, $[[T0]]
56 ; MM32R3: movn $[[T1:[0-9]+]], $5, $[[T0]] # <MCInst #{{[0-9]+}} MOVN_I_MM
83 ; CMOV: movn $6, $5, $[[T0]]
92 ; MM32R3: movn $[[T1:[0-9]+]], $5, $[[T0]] # <MCInst #{{[0-9]+}} MOVN_I_MM
119 ; CMOV: movn $6, $5, $[[T0]]
129 ; MM32R3: movn $[[T1:[0-9]+]], $5, $[[T0]] # <MCInst #{{[0-9]+}} MOVN_I_MM
162 ; CMOV-32: movn $2, $6, $[[T0]]
164 ; CMOV-32: movn $3, $7, $[[T0]]
185 ; CMOV-64: movn $6, $5, $[[T0]]
197 ; MM32R3: movn $2, $6, $[[T0]] # <MCInst #{{[0-9]+}} MOVN_I_MM
[all …]
/external/llvm/test/CodeGen/Mips/llvm-ir/
Dselect-int.ll46 ; CMOV: movn $6, $5, $[[T0]]
55 ; MM32R3: movn $[[T1:[0-9]+]], $5, $[[T0]]
81 ; CMOV: movn $6, $5, $[[T0]]
90 ; MM32R3: movn $[[T1:[0-9]+]], $5, $[[T0]]
116 ; CMOV: movn $6, $5, $[[T0]]
125 ; MM32R3: movn $[[T1:[0-9]+]], $5, $[[T0]]
158 ; CMOV-32: movn $2, $6, $[[T0]]
160 ; CMOV-32: movn $3, $7, $[[T0]]
181 ; CMOV-64: movn $6, $5, $[[T0]]
193 ; MM32R3: movn $2, $6, $[[T0]]
[all …]
/external/llvm-project/llvm/test/CodeGen/Mips/Fast-ISel/
Dsel1.ll11 ; CHECK-NEXT: movn $6, $5, $1
29 ; CHECK-NEXT: movn $6, $5, $1
47 ; CHECK-NEXT: movn $6, $5, $1
63 ; CHECK-NEXT: movn $6, $5, $1
81 ; CHECK-NEXT: movn.s $f0, $f1, $1
96 ; CHECK-NEXT: movn.s $f0, $f12, $1
113 ; CHECK-NEXT: movn.d $f0, $f2, $1
129 ; CHECK-NEXT: movn.d $f0, $f12, $1
/external/llvm/test/CodeGen/Mips/Fast-ISel/
Dsel1.ll12 ; CHECK-NEXT: movn $6, $5, $[[T2]]
29 ; CHECK-NEXT: movn $6, $5, $[[T4]]
46 ; CHECK-NEXT: movn $6, $5, $[[T4]]
61 ; CHECK-NEXT: movn $6, $5, $[[T2]]
77 ; CHECK: movn.s $f0, $f1, $[[T2]]
93 ; CHECK: movn.d $f0, $f2, $[[T2]]
/external/llvm/test/MC/Mips/
Dmicromips-movcond-instructions.s13 # CHECK-EL: movn $9, $6, $7 # encoding: [0xe6,0x00,0x18,0x48]
20 # CHECK-EB: movn $9, $6, $7 # encoding: [0x00,0xe6,0x48,0x18]
24 movn $9, $6, $7
/external/llvm-project/llvm/test/CodeGen/Mips/
Dfunnel-shift-rot.ll85 ; CHECK-BE-NEXT: movn $8, $zero, $1
93 ; CHECK-BE-NEXT: movn $9, $10, $7
100 ; CHECK-BE-NEXT: movn $3, $6, $1
101 ; CHECK-BE-NEXT: movn $10, $zero, $7
113 ; CHECK-LE-NEXT: movn $8, $zero, $1
121 ; CHECK-LE-NEXT: movn $9, $10, $6
128 ; CHECK-LE-NEXT: movn $2, $7, $1
129 ; CHECK-LE-NEXT: movn $10, $zero, $6
263 ; CHECK-BE-NEXT: movn $8, $zero, $1
271 ; CHECK-BE-NEXT: movn $9, $10, $7
[all …]
Dzeroreg.ll16 ; 32-CMOV: movn $2, $zero, $4
22 ; 64-CMOV: movn $2, $zero, $4
63 ; 32-CMOV-DAG: movn $[[R0]], $zero, $4
64 ; 32-CMOV-DAG: movn $[[R1]], $zero, $4
73 ; 64-CMOV: movn $2, $zero, $4
Dcmov.ll16 ; 32-CMOV-DAG: movn $[[R0]], $[[R1]], $4
28 ; 64-CMOV-DAG: movn $[[R0]], $[[R1]], $4
56 ; 32-CMOV-DAG: movn $[[R1]], $[[R0]], $4
68 ; 64-CMOV: movn $[[R1]], $[[R0]], $4
128 ; 32-CMOV: movn ${{[26]}}, $5, $[[R1]]
138 ; 64-CMOV: movn ${{[26]}}, $5, $[[R1]]
200 ; 32-CMOV-DAG: movn $[[R2]], $6, $[[R1]]
201 ; 32-CMOV-DAG: movn $[[R3]], $7, $[[R1]]
216 ; 64-CMOV: movn ${{[26]}}, $5, $[[R1]]
279 ; 32-CMOV-DAG: movn $[[I5]], $[[I7]], $[[R0]]
[all …]
/external/llvm/test/CodeGen/Mips/
Dzeroreg.ll16 ; 32-CMOV: movn $2, $zero, $4
22 ; 64-CMOV: movn $2, $zero, $4
63 ; 32-CMOV-DAG: movn $[[R0]], $zero, $4
64 ; 32-CMOV-DAG: movn $[[R1]], $zero, $4
73 ; 64-CMOV: movn $2, $zero, $4
Dcmov.ll16 ; 32-CMOV-DAG: movn $[[R0]], $[[R1]], $4
28 ; 64-CMOV-DAG: movn $[[R0]], $[[R1]], $4
56 ; 32-CMOV-DAG: movn $[[R1]], $[[R0]], $4
68 ; 64-CMOV: movn $[[R1]], $[[R0]], $4
128 ; 32-CMOV: movn ${{[26]}}, $5, $[[R1]]
138 ; 64-CMOV: movn ${{[26]}}, $5, $[[R1]]
200 ; 32-CMOV-DAG: movn $[[R2]], $6, $[[R1]]
201 ; 32-CMOV-DAG: movn $[[R3]], $7, $[[R1]]
216 ; 64-CMOV: movn ${{[26]}}, $5, $[[R1]]
279 ; 32-CMOV-DAG: movn $[[I5]], $[[I7]], $[[R0]]
[all …]
/external/llvm-project/llvm/test/MC/Mips/
Dmicromips-movcond-instructions.s14 # CHECK-EL: movn $9, $6, $7 # encoding: [0xe6,0x00,0x18,0x48]
25 # CHECK-EB: movn $9, $6, $7 # encoding: [0x00,0xe6,0x48,0x18]
32 movn $9, $6, $7

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