| /external/mesa3d/src/amd/compiler/ |
| D | aco_print_ir.cpp | 365 const MUBUF_instruction* mubuf = static_cast<const MUBUF_instruction*>(instr); in print_instr_format_specific() local
366 if (mubuf->offset) in print_instr_format_specific()
367 fprintf(output, " offset:%u", mubuf->offset); in print_instr_format_specific()
368 if (mubuf->offen) in print_instr_format_specific()
370 if (mubuf->idxen) in print_instr_format_specific()
372 if (mubuf->addr64) in print_instr_format_specific()
374 if (mubuf->glc) in print_instr_format_specific()
376 if (mubuf->dlc) in print_instr_format_specific()
378 if (mubuf->slc) in print_instr_format_specific()
380 if (mubuf->tfe) in print_instr_format_specific()
[all …]
|
| D | aco_assembler.cpp | 361 MUBUF_instruction* mubuf = static_cast<MUBUF_instruction*>(instr); in emit_instruction() local
364 encoding |= (mubuf->lds ? 1 : 0) << 16; in emit_instruction()
365 encoding |= (mubuf->glc ? 1 : 0) << 14; in emit_instruction()
366 encoding |= (mubuf->idxen ? 1 : 0) << 13; in emit_instruction()
367 assert(!mubuf->addr64 || ctx.chip_class <= GFX7); in emit_instruction()
369 encoding |= (mubuf->addr64 ? 1 : 0) << 15; in emit_instruction()
370 encoding |= (mubuf->offen ? 1 : 0) << 12; in emit_instruction()
372 assert(!mubuf->dlc); /* Device-level coherent is not supported on GFX9 and lower */ in emit_instruction()
373 encoding |= (mubuf->slc ? 1 : 0) << 17; in emit_instruction()
375 encoding |= (mubuf->dlc ? 1 : 0) << 15; in emit_instruction()
[all …]
|
| D | aco_instruction_selection.cpp | 3437 aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(op, Format::MUBUF, 3, 1)}; in mubuf_load_callback() local
3438 mubuf->operands[0] = Operand(info.resource); in mubuf_load_callback()
3439 mubuf->operands[1] = vaddr; in mubuf_load_callback()
3440 mubuf->operands[2] = soffset; in mubuf_load_callback()
3441 mubuf->offen = (offset.type() == RegType::vgpr); in mubuf_load_callback()
3442 mubuf->glc = info.glc; in mubuf_load_callback()
3443 mubuf->dlc = info.glc && bld.program->chip_class >= GFX10; in mubuf_load_callback()
3444 mubuf->slc = info.slc; in mubuf_load_callback()
3445 mubuf->sync = info.sync; in mubuf_load_callback()
3446 mubuf->offset = const_offset; in mubuf_load_callback()
[all …]
|
| D | aco_optimizer.cpp | 965 MUBUF_instruction *mubuf = static_cast<MUBUF_instruction *>(instr.get()); in label_instruction() local
977 bool vaddr_prevent_overflow = mubuf->swizzled && ctx.program->chip_class < GFX9; in label_instruction()
978 bool saddr_prevent_overflow = mubuf->swizzled; in label_instruction()
980 …if (mubuf->offen && i == 1 && info.is_constant_or_literal(32) && mubuf->offset + info.val < 4096) { in label_instruction()
981 assert(!mubuf->idxen); in label_instruction()
983 mubuf->offset += info.val; in label_instruction()
984 mubuf->offen = false; in label_instruction()
986 } else if (i == 2 && info.is_constant_or_literal(32) && mubuf->offset + info.val < 4096) { in label_instruction()
988 mubuf->offset += info.val; in label_instruction()
990 …} else if (mubuf->offen && i == 1 && parse_base_offset(ctx, instr.get(), i, &base, &offset, vaddr_… in label_instruction()
[all …]
|
| D | aco_spill.cpp | 1592 …Instruction *instr = bld.mubuf(opcode, scratch_rsrc, Operand(v1), scratch_offset, split->definitio… in assign_spill_slots()
1596 …Instruction *instr = bld.mubuf(opcode, scratch_rsrc, Operand(v1), scratch_offset, temp, offset, fa… in assign_spill_slots()
1661 …Instruction *instr = bld.mubuf(opcode, Definition(tmp), scratch_rsrc, Operand(v1), scratch_offset,… in assign_spill_slots()
1666 …Instruction *instr = bld.mubuf(opcode, def, scratch_rsrc, Operand(v1), scratch_offset, offset, fal… in assign_spill_slots()
|
| D | aco_insert_exec_mask.cpp | 137 MUBUF_instruction *mubuf = static_cast<MUBUF_instruction *>(instr.get()); in needs_exact() local
138 return mubuf->disable_wqm; in needs_exact()
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | SIInstructions.td | 932 mubuf<0x00>, "buffer_load_format_x", VGPR_32
935 mubuf<0x01>, "buffer_load_format_xy", VReg_64
938 mubuf<0x02>, "buffer_load_format_xyz", VReg_96
941 mubuf<0x03>, "buffer_load_format_xyzw", VReg_128
944 mubuf<0x04>, "buffer_store_format_x", VGPR_32
947 mubuf<0x05>, "buffer_store_format_xy", VReg_64
950 mubuf<0x06>, "buffer_store_format_xyz", VReg_96
953 mubuf<0x07>, "buffer_store_format_xyzw", VReg_128
956 mubuf<0x08, 0x10>, "buffer_load_ubyte", VGPR_32, i32, mubuf_az_extloadi8
959 mubuf<0x09, 0x11>, "buffer_load_sbyte", VGPR_32, i32, mubuf_sextloadi8
[all …]
|
| D | SIInstrInfo.td | 2884 class mubuf <bits<7> si, bits<7> vi = si> {
2924 class MUBUF_Real_si <mubuf op, string opName, dag outs, dag ins,
2935 class MUBUF_Real_vi <mubuf op, string opName, dag outs, dag ins,
2946 multiclass MUBUF_m <mubuf op, string opName, dag outs, dag ins, string asm,
2959 multiclass MUBUFAddr64_m <mubuf op, string opName, dag outs,
2973 multiclass MUBUFAtomicOffset_m <mubuf op, string opName, dag outs, dag ins,
2989 multiclass MUBUFAtomicAddr64_m <mubuf op, string opName, dag outs, dag ins,
3004 multiclass MUBUFAtomicOther_m <mubuf op, string opName, dag outs, dag ins,
3019 multiclass MUBUF_Atomic <mubuf op, string name, RegisterClass rc,
3131 multiclass MUBUF_Load_Helper <mubuf op, string name, RegisterClass regClass,
[all …]
|
| D | CIInstructions.td | 104 defm BUFFER_WBINVL1_VOL : MUBUF_Invalidate <mubuf<0x70, 0x3f>,
|
| /external/llvm-project/llvm/test/CodeGen/AMDGPU/ |
| D | move-addr64-rsrc-dead-subreg-writes.ll | 3 ; Check that when mubuf addr64 instruction is handled in moveToVALU
|
| D | shader-addr64-nonuniform.ll | 6 ; addr64 mubuf with no readfirstlane.
|
| D | break-vmem-soft-clauses.mir | 434 # Break a clause from interference between mubuf and flat instructions
450 # Break a clause from interference between mubuf and flat instructions
529 # Make sure there is no assert on mubuf instructions which do not have
|
| D | scratch-buffer.ll | 5 ; it in mubuf's offset field.
|
| D | salu-to-valu.ll | 15 ; GCN-LABEL: {{^}}mubuf:
27 define amdgpu_kernel void @mubuf(i32 addrspace(1)* %out, i8 addrspace(1)* %in) #1 {
|
| D | cgp-addressing-modes.ll | 531 ; Address offset is not a multiple of 4. This is a valid mubuf offset,
|
| /external/llvm/test/CodeGen/AMDGPU/ |
| D | move-addr64-rsrc-dead-subreg-writes.ll | 3 ; Check that when mubuf addr64 instruction is handled in moveToVALU
|
| D | scratch-buffer.ll | 5 ; it in mubuf's offset field.
|
| D | salu-to-valu.ll | 15 ; GCN-LABEL: {{^}}mubuf:
27 define void @mubuf(i32 addrspace(1)* %out, i8 addrspace(1)* %in) #1 {
|
| D | min.ll | 72 ; extloads with mubuf instructions.
|
| /external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/ |
| D | smrd.ll | 1 ; FIXME: Need to add support for mubuf stores to enable this on SI.
|
| /external/llvm-project/mlir/test/Target/ |
| D | rocdl.mlir | 155 llvm.func @rocdl.mubuf(%rsrc : !llvm.vec<4 x i32>, %vindex : !llvm.i32,
159 // CHECK-LABEL: rocdl.mubuf
|
| /external/llvm-project/mlir/test/Dialect/LLVMIR/ |
| D | rocdl.mlir | 148 llvm.func @rocdl.mubuf(%rsrc : !llvm.vec<4 x i32>, %vindex : !llvm.i32,
152 // CHECK-LABEL: rocdl.mubuf
|
| /external/llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/ |
| D | split-gep-and-gvn-addrspace-addressing-modes.ll | 37 ; Some of the indices go over the maximum mubuf offset, so don't split them.
|
| /external/llvm-project/llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/ |
| D | split-gep-and-gvn-addrspace-addressing-modes.ll | 37 ; Some of the indices go over the maximum mubuf offset, so don't split them.
|
| /external/mesa3d/docs/relnotes/ |
| D | 20.3.0.rst | 4104 - aco: use mubuf helper in select_gs_copy_shader
|