Home
last modified time | relevance | path

Searched refs:mul (Results 1 – 25 of 4534) sorted by relevance

12345678910>>...182

/external/llvm-project/llvm/test/Analysis/ScalarEvolution/
Dpr18606.ll4 ; CHECK: %mul.lcssa5 = phi i32 [ %a.promoted4, %entry ], [ %mul.30, %for.body3 ]
5 ; CHECK: %mul = mul nsw i32 %mul.lcssa5, %mul.lcssa5
6 ; CHECK: %mul.30 = mul nsw i32 %mul.29, %mul.29
21 %mul.lcssa5 = phi i32 [ %a.promoted4, %entry ], [ %mul.30, %for.body3 ]
26 %mul = mul nsw i32 %mul.lcssa5, %mul.lcssa5
27 %mul.1 = mul nsw i32 %mul, %mul
28 %mul.2 = mul nsw i32 %mul.1, %mul.1
29 %mul.3 = mul nsw i32 %mul.2, %mul.2
30 %mul.4 = mul nsw i32 %mul.3, %mul.3
31 %mul.5 = mul nsw i32 %mul.4, %mul.4
[all …]
Dpr18606-min-zeros.ll5 ; CHECK: %37 = mul i32 %36, %36
27 %6 = mul i32 %5, %5
28 %7 = mul i32 %6, %6
29 %8 = mul i32 %7, %7
30 %9 = mul i32 %8, %8
31 %10 = mul i32 %9, %9
32 %11 = mul i32 %10, %10
33 %12 = mul i32 %11, %11
34 %13 = mul i32 %12, %12
35 %14 = mul i32 %13, %13
[all …]
Dmax-mulops-inline.ll14 ; CHECK1: %mul.1 = mul nsw i32 %mul, %mul
17 ; CHECK10: %mul.1 = mul nsw i32 %mul, %mul
22 %mul = mul nsw i32 %a.promoted, %a.promoted
23 %mul.1 = mul nsw i32 %mul, %mul
24 %mul.2 = mul nsw i32 %mul.1, %mul.1
25 %mul.3 = mul nsw i32 %mul.2, %mul.2
26 %mul.4 = mul nsw i32 %mul.3, %mul.3
27 %mul.5 = mul nsw i32 %mul.4, %mul.4
28 store i32 %mul.5, i32* @a, align 4
/external/llvm/test/Transforms/Reassociate/
Drepeats.ll40 %tmp1 = mul i8 3, 3
41 %tmp2 = mul i8 %tmp1, 3
42 %tmp3 = mul i8 %tmp2, 3
43 %tmp4 = mul i8 %tmp3, 3
51 ; CHECK-NEXT: mul
52 ; CHECK-NEXT: mul
54 %tmp1 = mul i3 %x, %x
55 %tmp2 = mul i3 %tmp1, %x
56 %tmp3 = mul i3 %tmp2, %x
57 %tmp4 = mul i3 %tmp3, %x
[all …]
Dmulfactor.ll5 ; CHECK: mul i32 %a, %a
6 ; CHECK-NEXT: mul i32 %a, 2
8 ; CHECK-NEXT: mul
13 %tmp.2 = mul i32 %a, %a
15 %tmp.6 = mul i32 %tmp.5, %b
16 %tmp.10 = mul i32 %b, %b
24 ; CHECK: mul
29 %a = mul i32 %t, 6
30 %b = mul i32 %t, 36
39 ; CHECK: mul
[all …]
Dmightymul.ll5 %t0 = mul i32 %x, %x
6 %t1 = mul i32 %t0, %t0
7 %t2 = mul i32 %t1, %t1
8 %t3 = mul i32 %t2, %t2
9 %t4 = mul i32 %t3, %t3
10 %t5 = mul i32 %t4, %t4
11 %t6 = mul i32 %t5, %t5
12 %t7 = mul i32 %t6, %t6
13 %t8 = mul i32 %t7, %t7
14 %t9 = mul i32 %t8, %t8
[all …]
/external/llvm-project/llvm/test/Transforms/Reassociate/
Drepeats.ll40 %tmp1 = mul i8 3, 3
41 %tmp2 = mul i8 %tmp1, 3
42 %tmp3 = mul i8 %tmp2, 3
43 %tmp4 = mul i8 %tmp3, 3
51 ; CHECK-NEXT: mul
52 ; CHECK-NEXT: mul
54 %tmp1 = mul i3 %x, %x
55 %tmp2 = mul i3 %tmp1, %x
56 %tmp3 = mul i3 %tmp2, %x
57 %tmp4 = mul i3 %tmp3, %x
[all …]
Dmulfactor.ll6 ; CHECK-NEXT: [[T2:%.*]] = mul i32 [[A:%.*]], [[A]]
7 ; CHECK-NEXT: [[T6:%.*]] = mul i32 [[A]], 2
9 ; CHECK-NEXT: [[REASS_MUL:%.*]] = mul i32 [[REASS_ADD]], [[B]]
13 %t2 = mul i32 %a, %a
15 %t6 = mul i32 %t5, %b
16 %t8 = mul i32 %b, %b
24 ; CHECK-NEXT: [[REASS_MUL:%.*]] = mul i32 [[T:%.*]], 42
28 %a = mul i32 %t, 6
29 %b = mul i32 %t, 36
38 ; CHECK-NEXT: [[TMP1:%.*]] = mul i32 [[X:%.*]], [[X]]
[all …]
Dmightymul.ll5 %t0 = mul i32 %x, %x
6 %t1 = mul i32 %t0, %t0
7 %t2 = mul i32 %t1, %t1
8 %t3 = mul i32 %t2, %t2
9 %t4 = mul i32 %t3, %t3
10 %t5 = mul i32 %t4, %t4
11 %t6 = mul i32 %t5, %t5
12 %t7 = mul i32 %t6, %t6
13 %t8 = mul i32 %t7, %t7
14 %t9 = mul i32 %t8, %t8
[all …]
/external/mesa3d/src/intel/tools/tests/gen6/
Dmul.asm1 mul(8) m3<1>F g2<8,8,1>F g8<8,8,1>F { align1 1Q };
2 mul(16) m5<1>F g2<8,8,1>F g14<8,8,1>F { align1 1H };
3 mul(8) g7<1>F g44<8,8,1>F g4.1<0,1,0>F { align1 1Q };
4 mul(16) g18<1>F g28<8,8,1>F g6.1<0,1,0>F { align1 1H };
5 mul(8) g39<1>.xD g28<4>.xD g5<0>.xD { align16 1Q };
6 mul(8) g39<1>.xD g39<4>.xD 2D { align16 1Q };
7 mul(8) g38<1>.xF g2<0>.yF g2<0>.yF { align16 1Q };
8 mul(8) m4<1>.xyF g6<4>.xyyyF 0x3f000000F /* 0.5F */ { align16 NoDDClr 1Q };
9 mul(8) g8<1>F g3<4>F 0x37800000F /* 1.52588e-05F */ { align16 1Q };
10 mul(8) g2<1>F g5<8,8,1>F 0x40490fdbF /* 3.14159F */ { align1 1Q };
[all …]
/external/llvm/test/Transforms/InstCombine/
Dvector-mul.ll8 %mul = mul <4 x i8> %InVec, <i8 0, i8 0, i8 0, i8 0>
9 ret <4 x i8> %mul
17 %mul = mul <4 x i8> %InVec, <i8 1, i8 1, i8 1, i8 1>
18 ret <4 x i8> %mul
26 %mul = mul <4 x i8> %InVec, <i8 2, i8 2, i8 2, i8 2>
27 ret <4 x i8> %mul
36 %mul = mul <4 x i8> %InVec, <i8 4, i8 4, i8 4, i8 4>
37 ret <4 x i8> %mul
46 %mul = mul <4 x i8> %InVec, <i8 8, i8 8, i8 8, i8 8>
47 ret <4 x i8> %mul
[all …]
/external/mesa3d/src/intel/tools/tests/gen7.5/
Dmul.asm1 mul(8) g45<1>.xF g5.4<0>.zF g5.4<0>.zF { align16 1Q };
2 mul(8) g18<1>F g17<4>F 0x3f000000F /* 0.5F */ { align16 1Q };
3 mul(8) g39<1>.xD g5<0>.xD 2D { align16 1Q };
4 mul(8) g7<1>F g39<8,8,1>F g4.1<0,1,0>F { align1 1Q };
5 mul(16) g19<1>F g37<8,8,1>F g6.1<0,1,0>F { align1 1H };
6 mul(8) acc0<1>UD g17<8,8,1>UD 0xaaaaaaabUD { align1 1Q };
7 mul(8) acc0<1>D g17<8,8,1>D 1431655766D { align1 1Q };
8 mul(8) g21<1>D g20<8,8,1>D 3W { align1 1Q };
9 mul(8) g7<1>F g5<8,8,1>F 0x3e800000F /* 0.25F */ { align1 1Q };
10 mul(8) acc0<1>UD g84<8,8,1>UD 0xaaaaaaabUD { align1 2Q };
[all …]
/external/mesa3d/src/intel/tools/tests/gen7/
Dmul.asm1 mul(8) g124<1>F g4<8,8,1>F g6<8,8,1>F { align1 1Q };
2 mul(16) g120<1>F g6<8,8,1>F g10<8,8,1>F { align1 1H };
3 mul(8) g45<1>.xF g5.4<0>.zF g5.4<0>.zF { align16 1Q };
4 mul(8) g39<1>.xD g5<0>.xD 2D { align16 1Q };
5 mul(8) acc0<1>D g5.4<0>.zwwwD g6<0>.xyyyD { align16 1Q };
6 mul(8) g124<1>F g4<8,8,1>F 0x3c23d70aF /* 0.01F */ { align1 1Q };
7 mul(16) g120<1>F g4<8,8,1>F 0x3c23d70aF /* 0.01F */ { align1 1H };
8 mul(8) g9<1>.xyF g8<4>.xyyyF 0x40000000F /* 2F */ { align16 1Q };
9 mul.sat(8) g19<1>.xyzF g15<4>.xyzzF g18<4>.xF { align16 1Q };
10 mul(8) g116<1>.xyF g6<4>.xyyyF 0x3f000000F /* 0.5F */ { align16 NoDDClr 1Q };
[all …]
/external/llvm/test/CodeGen/AArch64/
Dmul_pow2.ll3 ; Convert mul x, pow2 to shift.
4 ; Convert mul x, pow2 +/- 1 to shift + add/sub.
10 %mul = shl nsw i32 %x, 1
11 ret i32 %mul
18 %mul = mul nsw i32 %x, 3
19 ret i32 %mul
26 %mul = shl nsw i32 %x, 2
27 ret i32 %mul
35 %mul = mul nsw i32 %x, 5
36 ret i32 %mul
[all …]
/external/llvm/test/CodeGen/X86/
Dimul.ll10 %mul = mul i32 %A, 4
11 ret i32 %mul
20 %mul = mul i64 %A, 4
21 ret i64 %mul
29 %mul = mul i32 %A, 4096
30 ret i32 %mul
39 %mul = mul i64 %A, 4096
40 ret i64 %mul
50 %mul = mul i32 %A, -4096
51 ret i32 %mul
[all …]
/external/mesa3d/src/intel/tools/tests/gen4/
Dmul.asm1 mul(16) g16<1>F g14<8,8,1>F g12<8,8,1>F { align1 compr };
2 mul(8) g8<1>.xyzF g6<4>.xyzzF g8<4>.wF { align16 };
3 mul(8) g9<1>.wUD g7<4>.wF 0x45000000F /* 2048F */ { align16 };
4 mul(8) g8<1>.xD g8<4>.xD g5<0>.xD { align16 };
5 mul(8) g8<1>.xD g8<4>.xD 32D { align16 };
6 mul(16) m2<1>F g4<8,8,1>F g8.3<0,1,0>F { align1 compr };
7 mul(16) g22<1>F g16<8,8,1>F 0x41800000F /* 16F */ { align1 compr };
8 mul(8) m5<1>.xyF g3<4>.xyyyF 0x3f000000F /* 0.5F */ { align16 NoDDClr };
9 mul(8) g5<1>F g3<4>F 0x37800000F /* 1.52588e-05F */ { align16 };
10 mul.sat(16) m2<1>F g16<8,8,1>F g6<8,8,1>F { align1 compr };
[all …]
/external/mesa3d/src/intel/tools/tests/gen4.5/
Dmul.asm1 mul(16) m3<1>F g10<8,8,1>F g12<8,8,1>F { align1 compr4 };
2 mul(8) g8<1>.xyzF g6<4>.xyzzF g8<4>.wF { align16 };
3 mul(8) g9<1>.wUD g7<4>.wF 0x45000000F /* 2048F */ { align16 };
4 mul(16) g22<1>F g18<8,8,1>F g20<8,8,1>F { align1 compr };
5 mul(8) g8<1>.xD g8<4>.xD g5<0>.xD { align16 };
6 mul(8) g8<1>.xD g8<4>.xD 32D { align16 };
7 mul(16) g22<1>F g16<8,8,1>F 0x41800000F /* 16F */ { align1 compr };
8 mul(16) m3<1>F g6<8,8,1>F 0x3b800000F /* 0.00390625F */ { align1 compr4 };
9 mul(8) m5<1>.xyF g3<4>.xyyyF 0x3f000000F /* 0.5F */ { align16 NoDDClr };
10 mul(8) g5<1>F g3<4>F 0x37800000F /* 1.52588e-05F */ { align16 };
[all …]
/external/mesa3d/src/intel/tools/tests/gen5/
Dmul.asm1 mul(8) m3<1>F g3<8,8,1>F g2<8,8,1>F { align1 };
2 mul(16) m3<1>F g10<8,8,1>F g12<8,8,1>F { align1 compr4 };
3 mul(8) g8<1>.xyzF g6<4>.xyzzF g8<4>.wF { align16 };
4 mul(8) g9<1>.wUD g7<4>.wF 0x45000000F /* 2048F */ { align16 };
5 mul(8) g2<1>F g2<8,8,1>F g6.3<0,1,0>F { align1 };
6 mul(16) g10<1>F g12<8,8,1>F g6.3<0,1,0>F { align1 compr };
7 mul(8) g2<1>.xD g2<4>.xD g1<0>.xD { align16 };
8 mul(8) g5<1>F g3<8,8,1>F 0x41800000F /* 16F */ { align1 };
9 mul(8) m3<1>F g8<8,8,1>F 0x3b800000F /* 0.00390625F */ { align1 };
10 mul(16) g22<1>F g16<8,8,1>F 0x41800000F /* 16F */ { align1 compr };
[all …]
/external/llvm-project/llvm/test/Transforms/InstCombine/
Dvector-mul.ll13 %mul = mul <4 x i8> %InVec, <i8 0, i8 0, i8 0, i8 0>
14 ret <4 x i8> %mul
23 %mul = mul <4 x i8> %InVec, <i8 1, i8 1, i8 1, i8 1>
24 ret <4 x i8> %mul
34 %mul = mul <4 x i8> %InVec, <i8 2, i8 2, i8 2, i8 2>
35 ret <4 x i8> %mul
45 %mul = mul <4 x i8> %InVec, <i8 4, i8 4, i8 4, i8 4>
46 ret <4 x i8> %mul
56 %mul = mul <4 x i8> %InVec, <i8 8, i8 8, i8 8, i8 8>
57 ret <4 x i8> %mul
[all …]
/external/llvm-project/llvm/test/Analysis/CostModel/AMDGPU/
Dmul.ll7 ; THRPTALL: estimated cost of 4 for {{.*}} mul i32
8 ; SIZEALL: estimated cost of 2 for {{.*}} mul i32
11 %mul = mul i32 %vec, %b
12 store i32 %mul, i32 addrspace(1)* %out
17 ; THRPTALL: estimated cost of 8 for {{.*}} mul <2 x i32>
18 ; SIZEALL: estimated cost of 4 for {{.*}} mul <2 x i32>
21 %mul = mul <2 x i32> %vec, %b
22 store <2 x i32> %mul, <2 x i32> addrspace(1)* %out
27 ; THRPTALL: estimated cost of 12 for {{.*}} mul <3 x i32>
28 ; SIZEALL: estimated cost of 6 for {{.*}} mul <3 x i32>
[all …]
/external/libaom/libaom/aom_dsp/
Dfft_common.h142 #define GEN_FFT_8(ret, suffix, T, T_VEC, load, store, constant, add, sub, mul) \ argument
167 store(output + 1 * stride, add(w1, mul(kWeight2, sub(w8, w10)))); \
169 store(output + 3 * stride, sub(w1, mul(kWeight2, sub(w8, w10)))); \
172 sub(sub(kWeight0, w3), mul(kWeight2, add(w10, w8)))); \
174 store(output + 7 * stride, sub(w3, mul(kWeight2, add(w10, w8)))); \
178 mul) \ argument
214 const T_VEC w16[2] = { add(w1, mul(kWeight2, sub(w8, w10))), \
216 mul(kWeight2, add(w10, w8))) }; \
217 const T_VEC w18[2] = { sub(w1, mul(kWeight2, sub(w8, w10))), \
218 sub(w3, mul(kWeight2, add(w10, w8))) }; \
[all …]
/external/llvm/test/CodeGen/SystemZ/
Dint-mul-06.ll10 %mul = mul i64 %a, 2
11 ret i64 %mul
19 %mul = mul i64 %a, 3
20 ret i64 %mul
28 %mul = mul i64 %a, 32767
29 ret i64 %mul
37 %mul = mul i64 %a, 32768
38 ret i64 %mul
46 %mul = mul i64 %a, 32769
47 ret i64 %mul
[all …]
Dint-mul-05.ll10 %mul = mul i32 %a, 2
11 ret i32 %mul
19 %mul = mul i32 %a, 3
20 ret i32 %mul
28 %mul = mul i32 %a, 32767
29 ret i32 %mul
37 %mul = mul i32 %a, 32768
38 ret i32 %mul
46 %mul = mul i32 %a, 32769
47 ret i32 %mul
[all …]
/external/llvm-project/llvm/test/CodeGen/SystemZ/
Dint-mul-05.ll10 %mul = mul i32 %a, 2
11 ret i32 %mul
19 %mul = mul i32 %a, 3
20 ret i32 %mul
28 %mul = mul i32 %a, 32767
29 ret i32 %mul
37 %mul = mul i32 %a, 32768
38 ret i32 %mul
46 %mul = mul i32 %a, 32769
47 ret i32 %mul
[all …]
Dint-mul-06.ll10 %mul = mul i64 %a, 2
11 ret i64 %mul
19 %mul = mul i64 %a, 3
20 ret i64 %mul
28 %mul = mul i64 %a, 32767
29 ret i64 %mul
37 %mul = mul i64 %a, 32768
38 ret i64 %mul
46 %mul = mul i64 %a, 32769
47 ret i64 %mul
[all …]

12345678910>>...182