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Searched refs:next_insn_offset (Results 1 – 13 of 13) sorted by relevance

/external/igt-gpu-tools/assembler/
Dbrw_eu_compact.c676 int compacted_counts[p->next_insn_offset / 8]; in brw_compact_instructions()
680 int old_ip[p->next_insn_offset / 8]; in brw_compact_instructions()
742 p->next_insn_offset = offset; in brw_compact_instructions()
743 for (offset = 0; offset < p->next_insn_offset;) { in brw_compact_instructions()
783 if (p->next_insn_offset & 8) { in brw_compact_instructions()
788 p->next_insn_offset += 8; in brw_compact_instructions()
790 p->nr_insn = p->next_insn_offset / 16; in brw_compact_instructions()
794 brw_dump_compile(p, stdout, 0, p->next_insn_offset); in brw_compact_instructions()
797 for (offset = 0; offset < p->next_insn_offset;) { in brw_compact_instructions()
Dbrw_eu.c227 *sz = p->next_insn_offset; in brw_get_program()
Dbrw_eu.h53 unsigned int next_insn_offset; member
Dbrw_eu_emit.c765 p->next_insn_offset += 16; in brw_next_insn()
2390 for (ip = next_ip(p, start); ip < p->next_insn_offset; ip = next_ip(p, ip)) { in brw_find_next_block_end()
2420 for (ip = next_ip(p, start); ip < p->next_insn_offset; ip = next_ip(p, ip)) { in brw_find_loop_end()
2448 for (ip = 0; ip < p->next_insn_offset; ip = next_ip(p, ip)) { in brw_set_uip_jip()
/external/mesa3d/src/intel/compiler/
Dbrw_eu.cpp362 *sz = p->next_insn_offset; in brw_get_program()
396 p->nr_insn -= (p->next_insn_offset - start_offset) / sizeof(brw_inst); in brw_try_override_assembly()
399 p->next_insn_offset = start_offset + sb.st_size; in brw_try_override_assembly()
401 p->store = (brw_inst *)reralloc_size(p->mem_ctx, p->store, p->next_insn_offset); in brw_try_override_assembly()
412 start_offset, p->next_insn_offset, in brw_try_override_assembly()
Dbrw_fs_generator.cpp1884 int start_offset = p->next_insn_offset; in generate_code()
1903 unsigned int last_insn_offset = p->next_insn_offset; in generate_code()
1922 last_insn_offset = p->next_insn_offset; in generate_code()
1940 last_insn_offset = p->next_insn_offset; in generate_code()
1949 disasm_annotate(disasm_info, inst, p->next_insn_offset); in generate_code()
2607 assert(p->next_insn_offset == last_insn_offset + 16 || in generate_code()
2625 disasm_new_inst_group(disasm_info, p->next_insn_offset); in generate_code()
2634 p->next_insn_offset, in generate_code()
2637 int before_size = p->next_insn_offset - start_offset; in generate_code()
2639 int after_size = p->next_insn_offset - start_offset; in generate_code()
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Dbrw_eu_compact.c2281 int compacted_counts[(p->next_insn_offset - start_offset) / sizeof(brw_inst)]; in brw_compact_instructions()
2285 int old_ip[(p->next_insn_offset - start_offset) / sizeof(brw_compact_inst) + 1]; in brw_compact_instructions()
2295 for (int src_offset = 0; src_offset < p->next_insn_offset - start_offset; in brw_compact_instructions()
2348 (p->next_insn_offset - start_offset) / sizeof(brw_inst); in brw_compact_instructions()
2351 p->next_insn_offset = start_offset + offset; in brw_compact_instructions()
2352 for (offset = 0; offset < p->next_insn_offset - start_offset; in brw_compact_instructions()
2438 if (p->next_insn_offset & sizeof(brw_compact_inst)) { in brw_compact_instructions()
2444 p->next_insn_offset += sizeof(brw_compact_inst); in brw_compact_instructions()
2446 p->nr_insn = p->next_insn_offset / sizeof(brw_inst); in brw_compact_instructions()
Dbrw_vec4_generator.cpp1497 disasm_annotate(disasm_info, inst, p->next_insn_offset); in generate_code()
2165 disasm_new_inst_group(disasm_info, p->next_insn_offset); in generate_code()
2173 0, p->next_insn_offset, in generate_code()
2176 int before_size = p->next_insn_offset; in generate_code()
2178 int after_size = p->next_insn_offset; in generate_code()
2184 _mesa_sha1_compute(p->store, p->next_insn_offset, sha1); in generate_code()
2200 dump_assembly(p->store, 0, p->next_insn_offset, in generate_code()
Dbrw_eu_emit.c665 assert(p->next_insn_offset == p->nr_insn * sizeof(brw_inst)); in brw_append_insns()
667 p->next_insn_offset = new_nr_insn * sizeof(brw_inst); in brw_append_insns()
2862 offset < p->next_insn_offset; in brw_find_next_block_end()
2911 offset < p->next_insn_offset; in brw_find_loop_end()
2939 for (offset = start_offset; offset < p->next_insn_offset; offset += 16) { in brw_set_uip_jip()
3681 .offset = p->next_insn_offset, in brw_MOV_reloc_imm()
Dtest_eu_validate.cpp105 disasm_new_inst_group(disasm, p->next_insn_offset); in validate()
109 p->next_insn_offset, disasm); in validate()
112 dump_assembly(p->store, 0, p->next_insn_offset, disasm, NULL); in validate()
128 p->next_insn_offset = 0; in clear_instructions()
Dbrw_eu.h93 unsigned int next_insn_offset; member
/external/mesa3d/src/intel/tools/
Di965_asm.c335 p->next_insn_offset, disasm_info); in main()
337 const int nr_insn = (p->next_insn_offset - start_offset) / 16; in main()
Di965_gram.y323 label->offset = p->next_insn_offset; in add_label()
1492 label->offset = p->next_insn_offset;