| /external/mesa3d/src/panfrost/util/ |
| D | pan_lower_framebuffer.c | 327 nir_imm_ivec4(b, 4, 4, 4, 4)); in pan_pack_unorm_4()
335 nir_imm_ivec4(b, 4, 4, 4, 4)); in pan_unpack_unorm_4()
345 nir_imm_ivec4(b, 3, 3, 3, 7)); in pan_pack_unorm_5551()
353 nir_imm_ivec4(b, 3, 3, 3, 7)); in pan_unpack_unorm_5551()
361 nir_imm_ivec4(b, 3, 2, 3, 0)); in pan_pack_unorm_565()
369 nir_imm_ivec4(b, 3, 2, 3, 0)); in pan_unpack_unorm_565()
382 nir_ssa_def *top8 = nir_ushr(b, s, nir_imm_ivec4(b, 0x2, 0x2, 0x2, 0x2)); in pan_pack_unorm_1010102()
385 nir_ssa_def *bottom2 = nir_iand(b, s, nir_imm_ivec4(b, 0x3, 0x3, 0x3, 0x3)); in pan_pack_unorm_1010102()
408 nir_imm_ivec4(b, 0, 2, 4, 6)); in pan_unpack_unorm_1010102()
410 nir_i2imp(b, nir_imm_ivec4(b, 0x3, 0x3, 0x3, 0x3))); in pan_unpack_unorm_1010102()
[all …]
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| /external/mesa3d/src/intel/compiler/ |
| D | brw_nir_attribute_workarounds.c | 77 nir_ssa_def *shift = nir_imm_ivec4(b, 22, 22, 22, 30); in apply_attr_wa_block()
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| /external/mesa3d/src/gallium/drivers/panfrost/nir/ |
| D | nir_lower_blend.c | 177 return nir_imm_ivec4(b, 0, 0, 0, 0); in nir_logicop_func()
207 return nir_imm_ivec4(b, ~0, ~0, ~0, ~0); in nir_logicop_func()
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| /external/mesa3d/src/amd/vulkan/ |
| D | radv_meta_buffer.c | 20 nir_ssa_def *block_size = nir_imm_ivec4(&b, in build_buffer_fill_shader()
68 nir_ssa_def *block_size = nir_imm_ivec4(&b, in build_buffer_copy_shader()
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| D | radv_meta_bufimage.c | 64 nir_ssa_def *block_size = nir_imm_ivec4(&b, in build_nir_itob_compute_shader()
293 nir_ssa_def *block_size = nir_imm_ivec4(&b, in build_nir_btoi_compute_shader()
515 nir_ssa_def *block_size = nir_imm_ivec4(&b, in build_nir_btoi_r32g32b32_compute_shader()
723 nir_ssa_def *block_size = nir_imm_ivec4(&b, in build_nir_itoi_compute_shader()
940 nir_ssa_def *block_size = nir_imm_ivec4(&b, in build_nir_itoi_r32g32b32_compute_shader()
1147 nir_ssa_def *block_size = nir_imm_ivec4(&b, in build_nir_cleari_compute_shader()
1339 nir_ssa_def *block_size = nir_imm_ivec4(&b, in build_nir_cleari_r32g32b32_compute_shader()
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| D | radv_meta_fmask_expand.c | 62 nir_ssa_def *block_size = nir_imm_ivec4(&b, in build_fmask_expand_compute_shader()
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| D | radv_query.c | 178 nir_ssa_def *block_size = nir_imm_ivec4(&b, in build_occlusion_query_shader()
342 nir_ssa_def *block_size = nir_imm_ivec4(&b, in build_pipeline_statistics_query_shader()
548 nir_ssa_def *block_size = nir_imm_ivec4(&b, in build_tfb_query_shader()
723 nir_ssa_def *block_size = nir_imm_ivec4(&b, in build_timestamp_query_shader()
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| D | radv_meta_resolve_cs.c | 97 nir_ssa_def *block_size = nir_imm_ivec4(&b, in build_resolve_compute_shader()
199 nir_ssa_def *block_size = nir_imm_ivec4(&b, in build_depth_stencil_resolve_compute_shader()
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| D | radv_meta_fast_clear.c | 62 nir_ssa_def *block_size = nir_imm_ivec4(&b, in build_dcc_decompress_compute_shader()
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| D | radv_meta_clear.c | 1179 nir_ssa_def *block_size = nir_imm_ivec4(&b, in build_clear_htile_mask_shader()
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| /external/mesa3d/src/compiler/nir/tests/ |
| D | vars_tests.cpp | 1780 nir_store_var(b, out, nir_imm_ivec4(b, 0, 0, 0, 0), 1 << 0); in TEST_F()
1781 nir_store_var(b, out, nir_imm_ivec4(b, 1, 1, 1, 1), 1 << 1); in TEST_F()
1782 nir_store_var_volatile(b, out, nir_imm_ivec4(b, -1, -2, -3, -4), 0xf); in TEST_F()
1783 nir_store_var(b, out, nir_imm_ivec4(b, 2, 2, 2, 2), 1 << 2); in TEST_F()
1784 nir_store_var(b, out, nir_imm_ivec4(b, 3, 3, 3, 3), 1 << 3); in TEST_F()
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| /external/mesa3d/src/gallium/drivers/r600/sfn/ |
| D | sfn_nir_lower_tess_io.cpp | 128 case 4: return nir_imm_ivec4(b, 0, 4, 8, 12); in load_offset_group()
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| D | sfn_nir.cpp | 650 addr = nir_iadd(&b, addr, nir_imm_ivec4(&b, 0, 4, 8, 12)); in r600_lower_shared_io_impl()
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| /external/mesa3d/src/compiler/nir/ |
| D | nir_builder.h | 400 nir_imm_ivec4(nir_builder *build, int x, int y, int z, int w) in nir_imm_ivec4() function
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