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/external/llvm-project/llvm/test/MC/Mips/msa/
Dtest_2r.s6 # CHECK: nloc.b $w21, $w0 # encoding: [0x7b,0x08,0x05,0x5e]
7 # CHECK: nloc.h $w18, $w31 # encoding: [0x7b,0x09,0xfc,0x9e]
8 # CHECK: nloc.w $w2, $w23 # encoding: [0x7b,0x0a,0xb8,0x9e]
9 # CHECK: nloc.d $w4, $w10 # encoding: [0x7b,0x0b,0x51,0x1e]
22 nloc.b $w21, $w0
23 nloc.h $w18, $w31
24 nloc.w $w2, $w23
25 nloc.d $w4, $w10
/external/llvm/test/MC/Mips/msa/
Dtest_2r.s6 # CHECK: nloc.b $w21, $w0 # encoding: [0x7b,0x08,0x05,0x5e]
7 # CHECK: nloc.h $w18, $w31 # encoding: [0x7b,0x09,0xfc,0x9e]
8 # CHECK: nloc.w $w2, $w23 # encoding: [0x7b,0x0a,0xb8,0x9e]
9 # CHECK: nloc.d $w4, $w10 # encoding: [0x7b,0x0b,0x51,0x1e]
22 nloc.b $w21, $w0
23 nloc.h $w18, $w31
24 nloc.w $w2, $w23
25 nloc.d $w4, $w10
/external/capstone/suite/MC/Mips/
Dtest_2r.s.cs5 0x7b,0x08,0x05,0x5e = nloc.b $w21, $w0
6 0x7b,0x09,0xfc,0x9e = nloc.h $w18, $w31
7 0x7b,0x0a,0xb8,0x9e = nloc.w $w2, $w23
8 0x7b,0x0b,0x51,0x1e = nloc.d $w4, $w10
/external/llvm-project/llvm/test/MC/Disassembler/Mips/msa/
Dtest_2r.txt6 0x7b 0x08 0x05 0x5e # CHECK: nloc.b $w21, $w0
7 0x7b 0x09 0xfc 0x9e # CHECK: nloc.h $w18, $w31
8 0x7b 0x0a 0xb8 0x9e # CHECK: nloc.w $w2, $w23
9 0x7b 0x0b 0x51 0x1e # CHECK: nloc.d $w4, $w10
/external/llvm/test/MC/Disassembler/Mips/msa/
Dtest_2r.txt6 0x7b 0x08 0x05 0x5e # CHECK: nloc.b $w21, $w0
7 0x7b 0x09 0xfc 0x9e # CHECK: nloc.h $w18, $w31
8 0x7b 0x0a 0xb8 0x9e # CHECK: nloc.w $w2, $w23
9 0x7b 0x0b 0x51 0x1e # CHECK: nloc.d $w4, $w10
/external/llvm/test/CodeGen/Mips/msa/
D2r.ll12 %1 = tail call <16 x i8> @llvm.mips.nloc.b(<16 x i8> %0)
17 declare <16 x i8> @llvm.mips.nloc.b(<16 x i8>) nounwind
22 ; CHECK-DAG: nloc.b [[WD:\$w[0-9]+]], [[WS]]
33 %1 = tail call <8 x i16> @llvm.mips.nloc.h(<8 x i16> %0)
38 declare <8 x i16> @llvm.mips.nloc.h(<8 x i16>) nounwind
43 ; CHECK-DAG: nloc.h [[WD:\$w[0-9]+]], [[WS]]
54 %1 = tail call <4 x i32> @llvm.mips.nloc.w(<4 x i32> %0)
59 declare <4 x i32> @llvm.mips.nloc.w(<4 x i32>) nounwind
64 ; CHECK-DAG: nloc.w [[WD:\$w[0-9]+]], [[WS]]
75 %1 = tail call <2 x i64> @llvm.mips.nloc.d(<2 x i64> %0)
[all …]
/external/llvm-project/llvm/test/CodeGen/Mips/msa/
D2r.ll12 %1 = tail call <16 x i8> @llvm.mips.nloc.b(<16 x i8> %0)
17 declare <16 x i8> @llvm.mips.nloc.b(<16 x i8>) nounwind
22 ; CHECK-DAG: nloc.b [[WD:\$w[0-9]+]], [[WS]]
33 %1 = tail call <8 x i16> @llvm.mips.nloc.h(<8 x i16> %0)
38 declare <8 x i16> @llvm.mips.nloc.h(<8 x i16>) nounwind
43 ; CHECK-DAG: nloc.h [[WD:\$w[0-9]+]], [[WS]]
54 %1 = tail call <4 x i32> @llvm.mips.nloc.w(<4 x i32> %0)
59 declare <4 x i32> @llvm.mips.nloc.w(<4 x i32>) nounwind
64 ; CHECK-DAG: nloc.w [[WD:\$w[0-9]+]], [[WS]]
75 %1 = tail call <2 x i64> @llvm.mips.nloc.d(<2 x i64> %0)
[all …]
/external/llvm-project/llvm/test/MC/Mips/mips32r2/
Dinvalid-msa.s48 …nloc.b $w12,$w30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU f…
49 …nloc.d $w16,$w7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU f…
50 …nloc.h $w21,$w17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU f…
51 …nloc.w $w17,$w16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU f…
/external/llvm/test/MC/Mips/mips32r2/
Dinvalid-msa.s48 …nloc.b $w12,$w30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU f…
49 …nloc.d $w16,$w7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU f…
50 …nloc.h $w21,$w17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU f…
51 …nloc.w $w17,$w16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU f…
/external/elfutils/libdw/
Ddwarf_getlocation.c216 newp->nloc = 1; in is_constant_offset()
221 assert ((*found)->nloc == 1); in is_constant_offset()
254 *listlen = (*found)->nloc; in __libdw_intern_expression()
636 newp->nloc = *listlen; in __libdw_intern_expression()
DlibdwP.h46 size_t nloc; member
/external/icu/icu4c/source/test/intltest/
Dsvccoll.cpp191 Locale nloc = ncol->getLocale(ULOC_VALID_LOCALE, status); in TestRegister() local
192 if (nloc != fu_FU) { in TestRegister()
193 … errln(UnicodeString("asked for nloc valid locale after close and got") + nloc.getName()); in TestRegister()
/external/python/setuptools/pkg_resources/
D__init__.py2733 nloc = _normalize_cached(loc)
2734 bdir = os.path.dirname(nloc)
2738 if item == nloc:
2748 if (not replace) and nloc in npath[p:]:
2753 npath.insert(p, nloc)
2767 np = npath.index(nloc, p + 1)
/external/elfutils/src/
Dnm.c600 size_t nloc; in get_var_range() local
601 if (dwarf_getlocation (locattr, &loc, &nloc) != 0) in get_var_range()
606 if (nloc == 1 && loc[0].atom == DW_OP_addr) in get_var_range()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsScheduleP5600.td428 // sll?.[bhwd], pckev.[bhwd], pckod.[bhwd], nloc.[bhwd], nlzc.[bhwd],
DMipsMSAInstrInfo.td2486 class NLOC_B_DESC : MSA_2R_DESC_BASE<"nloc.b", int_mips_nloc_b, MSA128BOpnd>;
2487 class NLOC_H_DESC : MSA_2R_DESC_BASE<"nloc.h", int_mips_nloc_h, MSA128HOpnd>;
2488 class NLOC_W_DESC : MSA_2R_DESC_BASE<"nloc.w", int_mips_nloc_w, MSA128WOpnd>;
2489 class NLOC_D_DESC : MSA_2R_DESC_BASE<"nloc.d", int_mips_nloc_d, MSA128DOpnd>;
DMipsScheduleGeneric.td1546 // sll?.[bhwd], pckev.[bhwd], pckod.[bhwd], nloc.[bhwd], nlzc.[bhwd],
/external/llvm-project/llvm/lib/Target/Mips/
DMipsScheduleP5600.td429 // sll?.[bhwd], pckev.[bhwd], pckod.[bhwd], nloc.[bhwd], nlzc.[bhwd],
DMipsMSAInstrInfo.td2496 class NLOC_B_DESC : MSA_2R_DESC_BASE<"nloc.b", int_mips_nloc_b, MSA128BOpnd>;
2497 class NLOC_H_DESC : MSA_2R_DESC_BASE<"nloc.h", int_mips_nloc_h, MSA128HOpnd>;
2498 class NLOC_W_DESC : MSA_2R_DESC_BASE<"nloc.w", int_mips_nloc_w, MSA128WOpnd>;
2499 class NLOC_D_DESC : MSA_2R_DESC_BASE<"nloc.d", int_mips_nloc_d, MSA128DOpnd>;
DMipsScheduleGeneric.td1549 // sll?.[bhwd], pckev.[bhwd], pckod.[bhwd], nloc.[bhwd], nlzc.[bhwd],
/external/llvm/lib/Target/Mips/
DMipsMSAInstrInfo.td2463 class NLOC_B_DESC : MSA_2R_DESC_BASE<"nloc.b", int_mips_nloc_b, MSA128BOpnd>;
2464 class NLOC_H_DESC : MSA_2R_DESC_BASE<"nloc.h", int_mips_nloc_h, MSA128HOpnd>;
2465 class NLOC_W_DESC : MSA_2R_DESC_BASE<"nloc.w", int_mips_nloc_w, MSA128WOpnd>;
2466 class NLOC_D_DESC : MSA_2R_DESC_BASE<"nloc.d", int_mips_nloc_d, MSA128DOpnd>;
/external/scapy/scapy/layers/
Dinet.py1070 self.nloc = None
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/
DMipsGenAsmMatcher.inc5062 "neg.s\004negu\006nloc.b\006nloc.d\006nloc.h\006nloc.w\006nlzc.b\006nlzc"
7297 …{ 7103 /* nloc.b */, Mips::NLOC_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasM…
7298 …{ 7110 /* nloc.d */, Mips::NLOC_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasM…
7299 …{ 7117 /* nloc.h */, Mips::NLOC_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasM…
7300 …{ 7124 /* nloc.w */, Mips::NLOC_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasM…
10772 { 7103 /* nloc.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10773 { 7110 /* nloc.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10774 { 7117 /* nloc.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10775 { 7124 /* nloc.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
/external/swiftshader/third_party/llvm-subzero/build/Android/include/llvm/IR/
DIntrinsics.gen2682 mips_nloc_b, // llvm.mips.nloc.b
2683 mips_nloc_d, // llvm.mips.nloc.d
2684 mips_nloc_h, // llvm.mips.nloc.h
2685 mips_nloc_w, // llvm.mips.nloc.w
8740 "llvm.mips.nloc.b",
8741 "llvm.mips.nloc.d",
8742 "llvm.mips.nloc.h",
8743 "llvm.mips.nloc.w",
16680 1, // llvm.mips.nloc.b
16681 1, // llvm.mips.nloc.d
[all …]
/external/swiftshader/third_party/llvm-subzero/build/Linux/include/llvm/IR/
DIntrinsics.gen2682 mips_nloc_b, // llvm.mips.nloc.b
2683 mips_nloc_d, // llvm.mips.nloc.d
2684 mips_nloc_h, // llvm.mips.nloc.h
2685 mips_nloc_w, // llvm.mips.nloc.w
8740 "llvm.mips.nloc.b",
8741 "llvm.mips.nloc.d",
8742 "llvm.mips.nloc.h",
8743 "llvm.mips.nloc.w",
16680 1, // llvm.mips.nloc.b
16681 1, // llvm.mips.nloc.d
[all …]

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