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Searched refs:num_dcc_levels (Results 1 – 7 of 7) sorted by relevance

/external/mesa3d/src/amd/common/
Dac_surface.c582 surf->num_dcc_levels = level + 1; in gfx6_compute_level()
635 surf->num_dcc_levels = 0; in gfx6_compute_level()
1035 surf->num_dcc_levels = 0; in gfx6_compute_surface()
1533 surf->num_dcc_levels = in->numMipLevels; in gfx9_compute_miptree()
1566 surf->num_dcc_levels = i + 1; in gfx9_compute_miptree()
1568 surf->num_dcc_levels = i; in gfx9_compute_miptree()
1573 if (!surf->num_dcc_levels) in gfx9_compute_miptree()
1582 if (in->flags.display && surf->num_dcc_levels && info->use_display_dcc_with_retile_blit) { in gfx9_compute_miptree()
1940 surf->num_dcc_levels = 0; in gfx9_compute_surface()
1989 if (surf->num_dcc_levels && in gfx9_compute_surface()
[all …]
Dac_surface.h201 unsigned num_dcc_levels : 4; member
/external/mesa3d/src/gallium/drivers/radeonsi/
Dsi_texture.c879 tex->surface.u.gfx9.display_dcc_pitch_max, tex->surface.num_dcc_levels); in si_print_texture_info()
928 i, i < tex->surface.num_dcc_levels, tex->surface.u.legacy.level[i].dcc_offset, in si_print_texture_info()
1115 if (tex->surface.num_dcc_levels == tex->buffer.b.b.last_level + 1 && in si_texture_create_object()
1134 for (unsigned i = 0; i < tex->surface.num_dcc_levels; i++) { in si_texture_create_object()
2166 assert(tex->surface.num_dcc_levels); in vi_separate_dcc_try_enable()
Dsi_pipe.h1588 return tex->surface.dcc_offset && level < tex->surface.num_dcc_levels; in vi_dcc_enabled()
Dsi_blit.c1276 for (unsigned level = 0; level < tex->surface.num_dcc_levels; level++) { in si_decompress_dcc()
/external/mesa3d/src/amd/vulkan/
Dradv_private.h1966 level < image->planes[0].surface.num_dcc_levels; in radv_dcc_enabled()
Dradv_cmd_buffer.c6036 for (unsigned i = 0; i < image->planes[0].surface.num_dcc_levels; i++) { in radv_initialize_dcc()