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Searched refs:num_reg (Results 1 – 11 of 11) sorted by relevance

/external/cpuinfo/test/dmesg/
Dzenfone-2.log51 [ 0.000000] gran_size: 64K chunk_size: 64K num_reg: 8 lose cover RAM: 3063M
52 [ 0.000000] gran_size: 64K chunk_size: 128K num_reg: 8 lose cover RAM: 3063M
53 [ 0.000000] gran_size: 64K chunk_size: 256K num_reg: 8 lose cover RAM: 3063M
54 [ 0.000000] gran_size: 64K chunk_size: 512K num_reg: 8 lose cover RAM: 3063M
55 [ 0.000000] gran_size: 64K chunk_size: 1M num_reg: 8 lose cover RAM: 3063M
56 [ 0.000000] gran_size: 64K chunk_size: 2M num_reg: 8 lose cover RAM: 3063M
57 [ 0.000000] gran_size: 64K chunk_size: 4M num_reg: 8 lose cover RAM: 3831M
58 [ 0.000000] gran_size: 64K chunk_size: 8M num_reg: 8 lose cover RAM: 3983M
59 [ 0.000000] gran_size: 64K chunk_size: 16M num_reg: 8 lose cover RAM: 3983M
60 [ 0.000000] gran_size: 64K chunk_size: 32M num_reg: 8 lose cover RAM: 3971M
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Dalldocube-iwork8.log130 <6>[ 0.000000] gran_size: 64K chunk_size: 64M num_reg: 5 lose cover RAM: 0G
/external/mesa3d/src/gallium/drivers/etnaviv/
Detnaviv_compiler_nir.c125 sf->reg[sf->num_reg].reg = src.reg; in etna_emit_output()
126 sf->reg[sf->num_reg].slot = var->data.location; in etna_emit_output()
127 sf->reg[sf->num_reg].num_components = glsl_get_components(var->type); in etna_emit_output()
128 sf->num_reg++; in etna_emit_output()
1008 v->input_count_unk8 = DIV_ROUND_UP(v->infile.num_reg + 4, 16); /* XXX what is this */ in fill_vs_mystery()
1029 int half_out = v->outfile.num_reg / 2 + 1; in fill_vs_mystery()
1077 sf->num_reg = MAX2(sf->num_reg, idx+1); in etna_compile_shader_nir()
1086 sf->num_reg = MAX2(sf->num_reg, idx+1); in etna_compile_shader_nir()
1089 assert(sf->num_reg == count); in etna_compile_shader_nir()
1191 for (int i = 0; i < sobj->outfile.num_reg; i++) in etna_shader_vs_lookup()
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Detnaviv_shader.c83 for (int idx = 0; idx < shader->infile.num_reg; ++idx) { in etna_dump_shader()
91 for (int idx = 0; idx < shader->outfile.num_reg; ++idx) { in etna_dump_shader()
323 num_vs_inputs = MAX2(ves->num_elements, vs->infile.num_reg); in etna_shader_update_vs_inputs()
326 ves->num_elements, vs->infile.num_reg); in etna_shader_update_vs_inputs()
331 num_temps = num_vs_inputs - vs->infile.num_reg + cur_temp; in etna_shader_update_vs_inputs()
341 if (idx < vs->infile.num_reg) in etna_shader_update_vs_inputs()
Detnaviv_compiler_tgsi.c2122 sf->num_reg = 0; in fill_in_ps_inputs()
2128 assert(sf->num_reg < ETNA_NUM_INPUTS); in fill_in_ps_inputs()
2129 sf->reg[sf->num_reg].reg = reg->native.id; in fill_in_ps_inputs()
2130 sf->reg[sf->num_reg].slot = sem2slot(&reg->semantic); in fill_in_ps_inputs()
2137 sf->reg[sf->num_reg].num_components = util_last_bit(reg->usage_mask); in fill_in_ps_inputs()
2138 sf->num_reg++; in fill_in_ps_inputs()
2142 assert(sf->num_reg == c->num_varyings); in fill_in_ps_inputs()
2150 sobj->outfile.num_reg = 0; in fill_in_ps_outputs()
2174 sf->num_reg = 0; in fill_in_vs_inputs()
2177 assert(sf->num_reg < ETNA_NUM_INPUTS); in fill_in_vs_inputs()
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Detnaviv_compiler.h67 size_t num_reg; member
Detnaviv_compiler_nir_ra.c211 reg = c->variant->infile.num_reg * NUM_REG_TYPES + REG_TYPE_VIRT_SCALAR_Y; in etna_ra_assign()
Detnaviv_nir.c116 v->vs_id_in_reg = v->infile.num_reg; in etna_lower_io()
/external/arm-trusted-firmware/plat/mediatek/mt8192/include/
Dplat_mt_cirq.h118 uint32_t num_reg; member
/external/mesa3d/src/gallium/drivers/lima/ir/gp/
Dnir.c404 static gpir_compiler *gpir_compiler_create(void *prog, unsigned num_reg, unsigned num_ssa) in gpir_compiler_create() argument
415 comp->node_for_reg = rzalloc_array(comp, gpir_node *, num_reg); in gpir_compiler_create()
417 comp->reg_for_reg = rzalloc_array(comp, gpir_reg *, num_reg); in gpir_compiler_create()
/external/mesa3d/src/gallium/drivers/lima/ir/pp/
Dnir.c772 static ppir_compiler *ppir_compiler_create(void *prog, unsigned num_reg, unsigned num_ssa) in ppir_compiler_create() argument
775 prog, sizeof(*comp) + ((num_reg << 2) + num_ssa) * sizeof(ppir_node *)); in ppir_compiler_create()