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Searched refs:num_scissors (Results 1 – 25 of 31) sorted by relevance

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/external/mesa3d/src/gallium/drivers/llvmpipe/
Dlp_state_clip.c67 unsigned num_scissors, in llvmpipe_set_scissor_states() argument
75 debug_assert((start_slot + num_scissors) <= PIPE_MAX_VIEWPORTS); in llvmpipe_set_scissor_states()
78 sizeof(struct pipe_scissor_state) * num_scissors); in llvmpipe_set_scissor_states()
/external/mesa3d/src/gallium/drivers/softpipe/
Dsp_state_clip.c67 unsigned num_scissors, in softpipe_set_scissor_states() argument
75 debug_assert((start_slot + num_scissors) <= PIPE_MAX_VIEWPORTS); in softpipe_set_scissor_states()
78 sizeof(struct pipe_scissor_state) * num_scissors); in softpipe_set_scissor_states()
/external/mesa3d/src/gallium/drivers/svga/
Dsvga_pipe_misc.c40 unsigned num_scissors, in svga_set_scissor_states() argument
47 assert(start_slot + num_scissors <= svgascreen->max_viewports); in svga_set_scissor_states()
49 for (i = 0, num_sc = start_slot; i < num_scissors; i++) { in svga_set_scissor_states()
/external/mesa3d/src/gallium/drivers/r600/
Dr600_viewport.c55 unsigned num_scissors, in r600_set_scissor_states() argument
61 for (i = 0; i < num_scissors; i++) in r600_set_scissor_states()
67 rctx->scissors.dirty_mask |= ((1 << num_scissors) - 1) << start_slot; in r600_set_scissor_states()
/external/virglrenderer/src/gallium/include/pipe/
Dp_context.h208 unsigned num_scissors,
/external/virglrenderer/tests/
Dtestvirgl_encode.h216 int num_scissors,
Dtestvirgl_encode.c754 int num_scissors, in virgl_encoder_set_scissor_state() argument
758 …word(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_SCISSOR_STATE, 0, VIRGL_SET_SCISSOR_STATE_SIZE(num_scissors))); in virgl_encoder_set_scissor_state()
760 for (i = 0; i < num_scissors; i++) { in virgl_encoder_set_scissor_state()
/external/mesa3d/src/gallium/auxiliary/driver_ddebug/
Ddd_context.c375 unsigned start_slot, unsigned num_scissors, in dd_context_set_scissor_states() argument
382 sizeof(*states) * num_scissors); in dd_context_set_scissor_states()
383 pipe->set_scissor_states(pipe, start_slot, num_scissors, states); in dd_context_set_scissor_states()
/external/mesa3d/src/gallium/auxiliary/driver_noop/
Dnoop_state.c141 unsigned num_scissors, in noop_set_scissor_states() argument
/external/mesa3d/src/gallium/drivers/radeonsi/
Dsi_state_viewport.c126 unsigned num_scissors, const struct pipe_scissor_state *state) in si_set_scissor_states() argument
131 for (i = 0; i < num_scissors; i++) in si_set_scissor_states()
/external/mesa3d/src/gallium/drivers/virgl/
Dvirgl_encode.h214 int num_scissors,
Dvirgl_encode.c1030 int num_scissors, in virgl_encoder_set_scissor_state() argument
1034 …word(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_SCISSOR_STATE, 0, VIRGL_SET_SCISSOR_STATE_SIZE(num_scissors))); in virgl_encoder_set_scissor_state()
1036 for (i = 0; i < num_scissors; i++) { in virgl_encoder_set_scissor_state()
/external/mesa3d/src/gallium/drivers/etnaviv/
Detnaviv_state.c376 unsigned num_scissors, const struct pipe_scissor_state *ss) in etna_set_scissor_states() argument
388 unsigned num_scissors, const struct pipe_viewport_state *vs) in etna_set_viewport_states() argument
/external/mesa3d/src/gallium/drivers/lima/
Dlima_state.c228 unsigned num_scissors, in lima_set_scissor_states() argument
/external/mesa3d/src/gallium/include/pipe/
Dp_context.h414 unsigned num_scissors,
/external/mesa3d/src/gallium/tools/trace/
Ddump_state.py406 def set_scissor_states(self, start_slot, num_scissors, states): argument
407 self._update(self._state.scissors, start_slot, num_scissors, states)
/external/mesa3d/src/gallium/drivers/nouveau/nv50/
Dnv50_state.c1017 unsigned num_scissors, in nv50_set_scissor_states() argument
1023 assert(start_slot + num_scissors <= NV50_MAX_VIEWPORTS); in nv50_set_scissor_states()
1024 for (i = 0; i < num_scissors; i++) { in nv50_set_scissor_states()
/external/mesa3d/src/gallium/auxiliary/driver_trace/
Dtr_context.c815 unsigned num_scissors, in trace_context_set_scissor_states() argument
825 trace_dump_arg(uint, num_scissors); in trace_context_set_scissor_states()
828 pipe->set_scissor_states(pipe, start_slot, num_scissors, states); in trace_context_set_scissor_states()
/external/mesa3d/src/gallium/drivers/nouveau/nvc0/
Dnvc0_state.c925 unsigned num_scissors, in nvc0_set_scissor_states() argument
931 assert(start_slot + num_scissors <= NVC0_MAX_VIEWPORTS); in nvc0_set_scissor_states()
932 for (i = 0; i < num_scissors; i++) { in nvc0_set_scissor_states()
/external/mesa3d/src/gallium/drivers/freedreno/
Dfreedreno_state.c283 unsigned num_scissors, in fd_set_scissor_states() argument
/external/mesa3d/src/gallium/drivers/vc4/
Dvc4_state.c293 unsigned num_scissors, in vc4_set_scissor_states() argument
/external/mesa3d/src/gallium/auxiliary/driver_rbug/
Drbug_context.c708 unsigned num_scissors, in rbug_set_scissor_states() argument
715 pipe->set_scissor_states(pipe, start_slot, num_scissors, scissor); in rbug_set_scissor_states()
/external/mesa3d/src/gallium/drivers/zink/
Dzink_context.c481 unsigned start_slot, unsigned num_scissors, in zink_set_scissor_states() argument
486 for (unsigned i = 0; i < num_scissors; i++) { in zink_set_scissor_states()
/external/mesa3d/src/gallium/drivers/panfrost/
Dpan_context.c1267 unsigned num_scissors, in panfrost_set_scissor_states() argument
1273 assert(num_scissors == 1); in panfrost_set_scissor_states()
/external/mesa3d/src/gallium/drivers/tegra/
Dtegra_context.c516 unsigned num_scissors, in tegra_set_scissor_states() argument
521 context->gpu->set_scissor_states(context->gpu, start_slot, num_scissors, in tegra_set_scissor_states()

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